Dual port RAM for Xilinx

T

Tobias Möglich

Guest
Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation". Is
there someone who knows about a complete design
for a dual port RAM.
I know, I need to get some more experience with VHDL.

Thank you for any help.

Tobias Möglich
 
Hello Tobias,

Tobias Möglich wrote:
Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation".
Click to expand...
I used that template without problems. But I assume that you can't use
single-bit signals as RAM-data-inputs.

some Code:

multibit <= singlebit1 & singlebit2;

RAM_P:pROCESS(clk)
BEGIN
if rising_edge(clk) then
if write = '1' then
ram(writeaddress) <= multibit;
end if;
readaddress <= read_address_in;
end if;
END PROCESS;

data_out <= ram(readaddress);

Synthesis now builds block RAM (synchronous read). For distributed RAM
read can be asynchronous.

HTH

Erik
--
\\Erik Markert - student of Information Technology//
\\ at Chemnitz University of Technology //
\\ TalkTo: erma@sirius.csn.tu-chemnitz.de //
\\ URL: http://www.erikmarkert.de //
 
Try Core Generator
"Tobias Möglich" <Tobias.Moeglich@gmx.net> Đ´ČëĎűϢĐÂÎĹ
:3FC23BDA.2A98A2BE@gmx.net...
Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation". Is
there someone who knows about a complete design
for a dual port RAM.
I know, I need to get some more experience with VHDL.

Thank you for any help.

Tobias Möglich
Click to expand...
 
Tobias,

Have you tried using the Xilinx Coregenerator to instantiate the Dual
port BRAM ?

-pradeep



Tobias Möglich wrote:

Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation". Is
there someone who knows about a complete design
for a dual port RAM.
I know, I need to get some more experience with VHDL.

Thank you for any help.

Tobias Möglich
Click to expand...
 
It is possible to use single bit signals al long as you define them as a
std_logic_vector (0 downto 0). This vector can be converted to a single
signal by the statement
signal <= vector(0);

Mark

"Erik Markert" <sirius571@gmx.net> schreef in bericht
news:bpv074$9aj$1@anderson.hrz.tu-chemnitz.de...
Hello Tobias,

Tobias Möglich wrote:
Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation".

I used that template without problems. But I assume that you can't use
single-bit signals as RAM-data-inputs.

some Code:

multibit <= singlebit1 & singlebit2;

RAM_P:pROCESS(clk)
BEGIN
if rising_edge(clk) then
if write = '1' then
ram(writeaddress) <= multibit;
end if;
readaddress <= read_address_in;
end if;
END PROCESS;

data_out <= ram(readaddress);

Synthesis now builds block RAM (synchronous read). For distributed RAM
read can be asynchronous.

HTH

Erik
--
\\Erik Markert - student of Information Technology//
\\ at Chemnitz University of Technology //
\\ TalkTo: erma@sirius.csn.tu-chemnitz.de //
\\ URL: http://www.erikmarkert.de //
Click to expand...
 
Hello!

Thank you for your advice. Yes, I tried it the CoreGenerator.
Hm. One more question:
Do I have to copy the source code generated by the CoreGenerator in a
vhd-file or
is it enough to add the generated core (-> including the xco-file by saying:
"New Source... IP(CoreGen & Architecture Wizard) in Xilinx ISE Foundation)?

Tobias

>
 
"Tobias Möglich" <Tobias.Moeglich@gmx.net> schreef in bericht
news:3FCB5117.960F18AA@gmx.net...
Hello!

Thank you for your advice. Yes, I tried it the CoreGenerator.
Hm. One more question:
Do I have to copy the source code generated by the CoreGenerator in a
vhd-file or
is it enough to add the generated core (-> including the xco-file by
saying:
"New Source... IP(CoreGen & Architecture Wizard) in Xilinx ISE
Foundation)?

Tobias
Click to expand...
The source code generated by the core generator is only needed for
simulation. You can just add the generated core to your project and create
an instance in the right HDL file or schematic

Mark
 
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