Dual Port RAM Block RAM using Core Generaot

[Tobias Möglich]

Hello

I'm using the core generator from Xilinx for installing a true dual port
RAM
But I wonder how I can handle it in the VHDL code ???
Could someone give me an advice??

This is what Iknow already:
Of course I put a component in the archticture (as I did it in the
example
below)

architecture Behavioral of dpram is
component dpram
port
(
addra: IN std_logic_VECTOR(8 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
dinb: INOUT std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(15 downto 0);
ena: IN std_logic;
enb: IN std_logic;
wea: IN std_logic;
web: IN std_logic
);
end component;

begin
-- Verwendung des cores (instantiation of the core)
dpram_block_1 : dpram -- dpram ist der component_name; dpram_block_1 ist

die Instanz
port map
(
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
ena => ena,
enb => enb,
wea => wea,
web => web
);


But how can I say where to store the values in the RAM ???
There must be something possible as described below:
But if I would use this code, I would not know where in the RAM the
values
are stored.

WRITE : process(clkb) -- Daten schreiben ins RAM (data -> ram)
begin
if rising_edge(clkb) then
if (cs_DSP = '0' and IORW_DSP = '1') then
-- Polarität prüfen
-- ram(conv_integer(addrb)) <= data_b;
-- von dinb in den Speicher (hoffentlich blockRAM !!)
dinb <= data_b;-- after 5 ns;
-- von dinb in den Speicher (hoffentlich blockRAM !!)
else dinb <= (others=>'Z'); --after 3 ns;
end if;
end if;
end process;


Do you have any example code??
It would be nice if you could send it to me just to get ahead.


MfG, Tobias Möglich.

 

[Tonny]

This is a dual port ram, then you have 2 ports... (duh!) port a and b.
in port a you have:
addra: IN std_logic_VECTOR(8 downto 0);
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
ena: IN std_logic;
wea: IN std_logic;

Where:
addra: is the address where you will store the data.
clka: is the clk
dina: is the data that will be store in the ram on address addra
douta: is the data stored in address addra
ena: enable the ram
wea: write the data DINA in address ADDRA, if asserted, else, read
the data
in address ADDRA and put in DOUTA

If you want write in RAM, you will assert WEA, put the address in
ADDRA, and the data in DINA, all in one clock.
If you want read, you will put the adrees in ADDRA, and read in
DOUTA.

Something this...

you can learn more in
http://direct.xilinx.com/bvdocs/appnotes/xapp173.pdf




Tobias Möglich <Tobias.Moeglich@gmx.net> wrote in message news:<3FFD80FE.9D9E69A4@gmx.net>...

Hello

I'm using the core generator from Xilinx for installing a true dual port
RAM
But I wonder how I can handle it in the VHDL code ???
Could someone give me an advice??

This is what Iknow already:
Of course I put a component in the archticture (as I did it in the
example
below)

architecture Behavioral of dpram is
component dpram
port
(
addra: IN std_logic_VECTOR(8 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
dinb: INOUT std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(15 downto 0);
ena: IN std_logic;
enb: IN std_logic;
wea: IN std_logic;
web: IN std_logic
);
end component;

begin
-- Verwendung des cores (instantiation of the core)
dpram_block_1 : dpram -- dpram ist der component_name; dpram_block_1 ist

die Instanz
port map
(
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
ena => ena,
enb => enb,
wea => wea,
web => web
);


But how can I say where to store the values in the RAM ???
There must be something possible as described below:
But if I would use this code, I would not know where in the RAM the
values
are stored.

WRITE : process(clkb) -- Daten schreiben ins RAM (data -> ram)
begin
if rising_edge(clkb) then
if (cs_DSP = '0' and IORW_DSP = '1') then
-- Polarität prüfen
-- ram(conv_integer(addrb)) <= data_b;
-- von dinb in den Speicher (hoffentlich blockRAM !!)
dinb <= data_b;-- after 5 ns;
-- von dinb in den Speicher (hoffentlich blockRAM !!)
else dinb <= (others=>'Z'); --after 3 ns;
end if;
end if;
end process;


Do you have any example code??
It would be nice if you could send it to me just to get ahead.


MfG, Tobias Möglich.

--