Dual Microblaze System

[alastair]

Hi,

I'm trying to build a system with Xilinx EDK 3.2 which will have 2
Microblaze processors running separate code on a Virtex-II
(xc2v-1000).

In XPS, each microblaze component is attached to it's own data and
instruction LMB's which have BRAM and BRAM controller blocks attached
in turn. When I attempt to generate the bitstream, the process fails
during the map stage. I get the following error message:

ERRORack:18 - The design is too large for the given device and
package.
Please check the Design Summary section to see which resource
requirement for
your design exceeds the resources available in the device.
..
..
..
Number of bonded IOBs: 132 out of 172 76%
Number of Tbufs: 1 out of 2,560 1%
Number of Block RAMs: 64 out of 40 160%
(OVERMAPPED)
Number of MULT18X18s: 6 out of 40 15%
Number of GCLKs: 1 out of 16 6%

So it looks to me like the number of block RAM's is where the problem
is. In the properties for each block ram, I've set the following
properties:
C_MEMSIZE = 8192
C_PORT_AWIDTH = 13

There is a total of 64k of block RAM available, so I figured that
allocating 8k to each processor should be fine.

If anyone has tried something similar I'd appreciate some ideas.

Thanks in advance,

Alastair.

 

[Shalin Sheth]

Alastair,

Check the memory mapping of all the Block RAM attached to the
processors. The mapping could be read from the following parameters of
the LMB Block RAM controllers:
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff

The above example is 8k of memory and will use 4 Block RAMs.

Shalin-

alastair wrote:

Hi,

I'm trying to build a system with Xilinx EDK 3.2 which will have 2
Microblaze processors running separate code on a Virtex-II
(xc2v-1000).

In XPS, each microblaze component is attached to it's own data and
instruction LMB's which have BRAM and BRAM controller blocks attached
in turn. When I attempt to generate the bitstream, the process fails
during the map stage. I get the following error message:

ERRORack:18 - The design is too large for the given device and
package.
Please check the Design Summary section to see which resource
requirement for
your design exceeds the resources available in the device.
.
.
.
Number of bonded IOBs: 132 out of 172 76%
Number of Tbufs: 1 out of 2,560 1%
Number of Block RAMs: 64 out of 40 160%
(OVERMAPPED)
Number of MULT18X18s: 6 out of 40 15%
Number of GCLKs: 1 out of 16 6%

So it looks to me like the number of block RAM's is where the problem
is. In the properties for each block ram, I've set the following
properties:
C_MEMSIZE = 8192
C_PORT_AWIDTH = 13

There is a total of 64k of block RAM available, so I figured that
allocating 8k to each processor should be fine.

If anyone has tried something similar I'd appreciate some ideas.

Thanks in advance,

Alastair.

 

[John Williams]

Hi Alistair,

alastair wrote:

I'm trying to build a system with Xilinx EDK 3.2 which will have 2
Microblaze processors running separate code on a Virtex-II
(xc2v-1000).

Firstly - if you possibly can, then upgrade to the latest version of
EDK. That's general advice, not specific to your question!

In XPS, each microblaze component is attached to it's own data and
instruction LMB's which have BRAM and BRAM controller blocks attached
in turn. When I attempt to generate the bitstream, the process fails
during the map stage. I get the following error message:

Number of Block RAMs: 64 out of 40 160%

So it looks to me like the number of block RAM's is where the problem
is. In the properties for each block ram, I've set the following
properties:
C_MEMSIZE = 8192
C_PORT_AWIDTH = 13

There is a total of 64k of block RAM available, so I figured that
allocating 8k to each processor should be fine.

Check to see if you are using caches for the microblaze - they are
implemented in BRAM. a 16K data and instruction cache will quickly chew
through your BRAM.

Also, if you grep through the *.srp files in the /synthesis project
subdirectory, you should be able to summarise the total BRAM usage:

Try this:

grep "Number.*BRAM" synthesis/*.srp

That will tell you exactly where you BRAM is going.

If anyone has tried something similar I'd appreciate some ideas.

I've built a dual processor microblaze system before (two microblazes on
the same OPB bus, shared memory etc) and it synthesised without any
troubles for the XC2V1000. I can dig out the project files if you are
interested.

Cheers,

John

 

[alastair]

Guys,

Thanks for the advice - we're intending to update to the latest
version of the tools soon

It's been a while since I did any development with XPS (that's my
excuse) and after checking the memory map for the BRAM controllers I
get past the error I saw. Now I get another one when generating the
bitstream:

ERROR:Ncd:528 - Could not find the the corresponding NC_COMP for the
BlockRAM
instancename:<bram_lmb_2/bram_block_0_i/ramb16_s9_s9_0>.Cannot
continue with
BlockRAM updates.
ERROR:Bitgen:194 - Unable to update BRAM initialization data for
design
system.ncd.
make: *** [implementation/system.bit] Error 1
Done.

John - if you have time to dig out your project with dual processors
I'd appreciate being able to have a look at the setup. I'm not sure
what the error means and can't seem to find any information on the
error from a quick search on Google and the Xilinx website - any ideas
?

Thanks again,

Alastair.

 

[John Williams]

Hi Alistair,

alastair wrote:

It's been a while since I did any development with XPS (that's my
excuse) and after checking the memory map for the BRAM controllers I
get past the error I saw. Now I get another one when generating the
bitstream:

ERROR:Ncd:528 - Could not find the the corresponding NC_COMP for the
BlockRAM
instancename:<bram_lmb_2/bram_block_0_i/ramb16_s9_s9_0>.Cannot
continue with
BlockRAM updates.
ERROR:Bitgen:194 - Unable to update BRAM initialization data for
design
system.ncd.
make: *** [implementation/system.bit] Error 1
Done.

Looks like the data2bram utility that stuffs bram contents onto the
bitstream, is having trouble distinguishing the various BRAMs. Did you
do a "make clean" after you fixed the initial error, and build it all
from scratch?

John - if you have time to dig out your project with dual processors
I'd appreciate being able to have a look at the setup. I'm not sure
what the error means and can't seem to find any information on the
error from a quick search on Google and the Xilinx website - any ideas

The MHS file is attached. This harwdare will build under 6.2, but I
don't think it will actually work. Note it's an SMP system, two
microblazes on the same bus which is not what you wanted. As such there
are other issues such as cache coherency (lack thereof), and no
interrupt sharing etc, but it's a starting point.

Cheers,

John

 

[alastair]

Hi John,

Thanks for posting the system - a combination of this and going
through my system with a careful eye got things working in the end
The final stumbling block was to make sure the reset signals for the
local memory buses were of the correct polarity.

Thanks again,

Alastair.