Dual clock FIFO with Atmel FPGA ??

[Fabio G.]

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL)
a dual clock FIFO (a FIFO with different read and write clock).
The problem is that the Atmel macro-generator has the ability to
generate only single clock FIFO.
Is it possible that Atmel did not think to include the possibility of
creating dual clock FIFO's in an efficient way???
Have I to design a FIFO by myself with "glue logic"?? In this way I
could not use the "FreeRAM" feature of the FPGA, and the resource use
would be critical.
Just to simulate my design, now I'm using a dual clock FIFO created with
the Altera macro generator, which uses a LPM_FIFO block. Do you think I
could try to synthesize this LPM_FIFO block in Atmel FPGA?


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[Peter Alfke]

A dual (uncorrelated) clock FIFO is infinitely more complex and tricky
than a single clock FIFO, which is just a synchronous state machine.
If theFIFO needs to run fast, then you need a dual-port RAM.
The problem with two asynchronous clocks is in the reliable detection of
FULL and EMPTY under all possible phase relationships of the two clocks.
See the Xilinx website for some ideas.
Peter Alfke, Xilinx
==============
"Fabio G." wrote:

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL)
a dual clock FIFO (a FIFO with different read and write clock).
The problem is that the Atmel macro-generator has the ability to
generate only single clock FIFO.
Is it possible that Atmel did not think to include the possibility of
creating dual clock FIFO's in an efficient way???
Have I to design a FIFO by myself with "glue logic"?? In this way I
could not use the "FreeRAM" feature of the FPGA, and the resource use
would be critical.
Just to simulate my design, now I'm using a dual clock FIFO created with
the Altera macro generator, which uses a LPM_FIFO block. Do you think I
could try to synthesize this LPM_FIFO block in Atmel FPGA?

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[Ulf Samuelsson]

"Fabio G." <9+3@supereva.it> skrev i meddelandet
news:40216cd1.24157170@powernews.libero.it...

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL)
a dual clock FIFO (a FIFO with different read and write clock).
The problem is that the Atmel macro-generator has the ability to
generate only single clock FIFO.
Is it possible that Atmel did not think to include the possibility of
creating dual clock FIFO's in an efficient way???
Have I to design a FIFO by myself with "glue logic"?? In this way I
could not use the "FreeRAM" feature of the FPGA, and the resource use
would be critical.
Just to simulate my design, now I'm using a dual clock FIFO created with
the Altera macro generator, which uses a LPM_FIFO block. Do you think I
could try to synthesize this LPM_FIFO block in Atmel FPGA?

The Leonardo synthesizer is normally smart enough to realize what you want
to do
if you describe a FIFO in HDL so it will use the FreeRAM which is Dual Port.
You can always instantiate the DPRAM and then generate stuff around it.

If/When you are stuck, fpslic at atmel dott com provides help
--
Best Regards,
Ulf Samuelsson ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB

 

[K Mussatt]

How fast are the two clocks relative to each other?

If one if much faster than the other use the 'fastest' one as the clock for
the entire FIFO
with the slower clock fed to an enable line so that when the slower clock
edge comes along
it will trigger it.

If the two clks are almost the same, you could use a 'master clock' (make
the whole thing sync
to this clk signal) and use the other two 'FI-clock' and 'FO-clock' 's as
enables. With this, you
should be able to sync up your RAMs and still with Atmel or anything else,
only use one 'master'
clk.

One finally suggestion: write your own FIFO don't use Atmel's (or any other
vendor). It is a bit
harder in the beginning, but if you must change chips, it is much easier to
do.

-Kip Mussatt


"Fabio G." <9+3@supereva.it> wrote in message
news:40216cd1.24157170@powernews.libero.it...

I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL)
a dual clock FIFO (a FIFO with different read and write clock).
The problem is that the Atmel macro-generator has the ability to
generate only single clock FIFO.
Is it possible that Atmel did not think to include the possibility of
creating dual clock FIFO's in an efficient way???
Have I to design a FIFO by myself with "glue logic"?? In this way I
could not use the "FreeRAM" feature of the FPGA, and the resource use
would be critical.
Just to simulate my design, now I'm using a dual clock FIFO created with
the Altera macro generator, which uses a LPM_FIFO block. Do you think I
could try to synthesize this LPM_FIFO block in Atmel FPGA?


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