DTB

P

parag

Guest
Dynamic Test Bench
Hi all
What is the scope for Dynamic Test bench systems
where suppose you aer in the debug environment of a simulation , you
are at time 10 , you need to write a new class, or extend on the
classes from your verification environment

Does a user require it, what is the potential for the same???
 
On Oct 14, 10:43 am, parag <parag.p...@gmail.com> wrote:

What is the scope for Dynamic Test bench systems
where suppose you aer in the debug environment of a simulation , you
are at time 10 , you need to write a new class, or extend on the
classes from your verification environment
Click to expand...
No! Defining or extending a class is something you can
do only at compile time.

Does a user require it, what is the potential for the same???
Click to expand...
Using class inheritance to add functionality dynamically
makes little sense. However, it might be reasonable to
make two versions of a class, with different functionality:

class C; // base class
...
endclass
class D extends C; ... endclass
class E extends C; ... endclass

Now you could imagine building a testbench that contains
a variable of type C. Using OVM's factory, or some similar
mechanism, you could arrange that the variable references
an object of type D at the start of simulation. Later in
the simulation, you could update the variable to reference
an object of type E. This is OK because C is the base
class for both D and E.

Getting this right is likely to be very difficult; it's
equivalent to rebuilding the testbench on-the-fly and
there are many issues about initialisation,
connection to the DUT and other parts of the TB, etc.

A better alternative might be to use some form of
callback. If properly designed, callbacks can easily
be replaced dynamically to change details of a testbench's
functionality during the life of the simulation. The VMM
testbench methodology has an explicit callback mechanism;
OVM also supports the same idea in different ways, and
there is a callback package available for OVM on the
ovmworld.org website (look for the "contributions" page).

Hope this helps
--
Jonathan Bromley
 
On Oct 14, 2:47 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
On Oct 14, 10:43 am, parag <parag.p...@gmail.com> wrote:

What is the scope for Dynamic Test bench systems
where suppose you aer in the debug environment of a simulation , you
are at time 10 , you need to write a new class, or extend on the
classes from your verification environment

No!  Defining or extending a class is something you can
do only at compile time.

Does a user require it, what is the potential for the same???

Using class inheritance to add functionality dynamically
makes little sense.  However, it might be reasonable to
make two versions of a class, with different functionality:

  class C; // base class
  ...
  endclass
  class D extends C; ... endclass
  class E extends C; ... endclass

Now you could imagine building a testbench that contains
a variable of type C.  Using OVM's factory, or some similar
mechanism, you could arrange that the variable references
an object of type D at the start of simulation.  Later in
the simulation, you could update the variable to reference
an object of type E.  This is OK because C is the base
class for both D and E.

Getting this right is likely to be very difficult; it's
equivalent to rebuilding the testbench on-the-fly and
there are many issues about initialisation,
connection to the DUT and other parts of the TB, etc.

A better alternative might be to use some form of
callback.  If properly designed, callbacks can easily
be replaced dynamically to change details of a testbench's
functionality during the life of the simulation.  The VMM
testbench methodology has an explicit callback mechanism;
OVM also supports the same idea in different ways, and
there is a callback package available for OVM on the
ovmworld.org website (look for the "contributions" page).

Hope this helps
--
Jonathan Bromley
Click to expand...
Thanks Jonathan
I am software engineer and understand very little of verification
I know that the problem is complex but solvable, we will try to get
this productizeed if we find it to be
useful to the customer.

It would be greatly appreciated if we could know real statistic of
whether customers want it or not

Or rather, I would ask you , that are there flows that you think are
missing in current solutions that we can look forward to solving

For me is a challenge to put in new flows and I would love to fix a
software problem of this complexity to be able to be of any hepl
to the verification enggs
 
On Oct 14, 12:59 pm, parag <parag.p...@gmail.com> wrote:
On Oct 14, 2:47 pm, Jonathan Bromley <s...@oxfordbromley.plus.com
wrote:



On Oct 14, 10:43 am, parag <parag.p...@gmail.com> wrote:

What is the scope for Dynamic Test bench systems
where suppose you aer in the debug environment of a simulation , you
are at time 10 , you need to write a new class, or extend on the
classes from your verification environment

No!  Defining or extending a class is something you can
do only at compile time.

Does a user require it, what is the potential for the same???

Using class inheritance to add functionality dynamically
makes little sense.  However, it might be reasonable to
make two versions of a class, with different functionality:

  class C; // base class
  ...
  endclass
  class D extends C; ... endclass
  class E extends C; ... endclass

Now you could imagine building a testbench that contains
a variable of type C.  Using OVM's factory, or some similar
mechanism, you could arrange that the variable references
an object of type D at the start of simulation.  Later in
the simulation, you could update the variable to reference
an object of type E.  This is OK because C is the base
class for both D and E.

Getting this right is likely to be very difficult; it's
equivalent to rebuilding the testbench on-the-fly and
there are many issues about initialisation,
connection to the DUT and other parts of the TB, etc.

A better alternative might be to use some form of
callback.  If properly designed, callbacks can easily
be replaced dynamically to change details of a testbench's
functionality during the life of the simulation.  The VMM
testbench methodology has an explicit callback mechanism;
OVM also supports the same idea in different ways, and
there is a callback package available for OVM on the
ovmworld.org website (look for the "contributions" page).

Hope this helps
--
Jonathan Bromley

Thanks Jonathan
I am software engineer and understand very little of verification
I know that the problem is complex but solvable, we will try to get
this productizeed if we find it to be
useful to the customer.

It would be greatly appreciated if we could know real statistic of
whether customers want it or not
Click to expand...
Sorry, I can't provide any useful input there.

Or rather, I would ask you , that are there flows that you think are
missing in current solutions that we can look forward to solving
Click to expand...
Well.... there are examples from other technologies ('e' language,
for example) that might be interesting in SV. How about
temporal assertions in classes? 'e' gets that right, but SV
assertions are designed to work well with formal verification
and so they don't fit nicely with classes.

Getting back to your original question, though, I can't help
feeling that it would be good to get aspect-oriented SV
stable and standardized before trying any new wild stuff
that doesn't have a secure theoretical background.

Thanks for the entertaining discussion!
--
Jonathan Bromley
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top