Driving INOUT signals

[Mike Nicklas]

Hi everyone

I'm trying to simulate a design using a testbench tool called HDL
bencher which is integrated with Xilinx ISE.

The problem i have is that when i set the value of the INOUT signal in
my design, the testbench does not appear to assert it as desired and the
port stays at value zero.

Has anyone else had any similar problems with HDL bencher and ISE?

Or does anyone have any recommendations / tips for working with INOUT
signals in designs?

Thanks in advance

Mike Nicklas

 

[MM]

"Mike Nicklas" <michaeln@nospamplease.slayer.com> wrote in message
news:403b1cd3$0$4101$5a6aecb4@news.aaisp.net.uk...

The problem i have is that when i set the value of the INOUT signal in
my design, the testbench does not appear to assert it as desired and the
port stays at value zero.

Can it be that you are initializing this signal in the test bench as zero?
Assuming the signal is std_logic try setting it to 'L' or 'Z' instead.


/Mikhail
--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")

 

[Mike Nicklas]

Hi

tried that too.

No joy unfortunately.

Any other ideas?

Regards

Mike

MM wrote:

"Mike Nicklas" <michaeln@nospamplease.slayer.com> wrote in message
news:403b1cd3$0$4101$5a6aecb4@news.aaisp.net.uk...

The problem i have is that when i set the value of the INOUT signal in
my design, the testbench does not appear to assert it as desired and the
port stays at value zero.


Can it be that you are initializing this signal in the test bench as zero?
Assuming the signal is std_logic try setting it to 'L' or 'Z' instead.


/Mikhail

 

[MM]

"Mike Nicklas" <michaeln@nospamplease.slayer.com> wrote in message
news:403c84b3$0$4103$5a6aecb4@news.aaisp.net.uk...

Hi

tried that too.

No joy unfortunately.

Any other ideas?

Post the relevant pieces of your code... Are you saying it works in another
simulator?

/Mikhail
--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")

 

[Mike Nicklas]

Hi

here is a copy of the top module entity declaration. The testbench i
tried was generated by a tool called HDL Bencher but i also tried using
the command line interface on ModelSIM XE to no avail.

entity nueping2 is
port ( -- Interface clock.
DSP_CLK: in STD_LOGIC;
-- Global reset.
RSTl: in STD_LOGIC;
-- Indicates whether Spartan can receive data.
BUSY: in STD_LOGIC;
-- Indicates whether Spartan has data to send.
EMPTY: in STD_LOGIC;
-- Indicates that ADIO is address or data.
AS_DSl: in STD_LOGIC;
-- Read/Write enable.
RENl_WENl: out STD_LOGIC;
-- Indicates if Spartan is being read or written to.
RDl_WR: out STD_LOGIC;
-- Interrupt to Spartan.
INTl: out STD_LOGIC;
-- Test LEDs.
LEDS: out STD_LOGIC_VECTOR (7 downto 0);
-- Data IO between Spartan and Virtex.
ADIO: inout STD_LOGIC_VECTOR (31 downto 0)
);
end nueping2;

I can add in the code from the auto-generated testbench as well if you like?

Mike

MM wrote:

"Mike Nicklas" <michaeln@nospamplease.slayer.com> wrote in message
news:403c84b3$0$4103$5a6aecb4@news.aaisp.net.uk...

Hi

tried that too.

No joy unfortunately.

Any other ideas?


Post the relevant pieces of your code... Are you saying it works in another
simulator?

/Mikhail

 

[MM]

here is a copy of the top module entity declaration.

This doesn't help much. We need to see how you drive the signal.

I can add in the code from the auto-generated testbench as well if you
like?

Yes, but only the lines relevant to the signal of interest...

/Mikhail
--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")

 

[Mike Nicklas]

sorry for the delay, have been off work.

-- --------------------
RSTl <= transport '1';
BUSY <= transport '0';
EMPTY <= transport '1';
AS_DSl <= transport '0';
ADIO <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
-- --------------------
WAIT FOR 4 ns; -- Time=4 ns
CHECK_ADIO("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ",4); --Z


that is the main set and check process used for the bidirectional signal
ADIO.

does this help?

Mike

MM wrote:

here is a copy of the top module entity declaration.


This doesn't help much. We need to see how you drive the signal.


I can add in the code from the auto-generated testbench as well if you

like?

Yes, but only the lines relevant to the signal of interest...

/Mikhail

 

[MM]

Mike,

Here is an example that works:
--------------------------------------------------
-- Entity Foo
--------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity foo is
port (
ADIO: inout STD_LOGIC
);
end foo;

architecture foo_behav of foo is
begin

process
begin
ADIO <= 'Z';
wait for 10 ns;
ADIO <= '1';
wait;
end process;

end foo_behav;
--------------------------------------------------
--
-- Title : Test Bench for Foo
--
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity foo_tb is
end foo_tb;

architecture TB_ARCHITECTURE of foo_tb is
component foo
port(
ADIO : inout std_logic
);
end component;

signal ADIO : std_logic;

begin

UUT : foo
port map (
ADIO => ADIO
);

adio <= 'Z';

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_foo of foo_tb is
for TB_ARCHITECTURE
for UUT : foo
use entity work.foo(foo_behav);
end for;
end for;
end TESTBENCH_FOR_foo;


I think your problem is that you are assigning the signal with a concurrent
statement in both your entity and the test bench. The simulator estimates
these only once and leaves the signal at the value that was assigned last...

/Mikhail