Driving fpga pin out over long cable

[Tom Derham]

I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to the
other boards, to allow them to synchronise internal timers. I need to make
sure that the pulse arrives at the other two boards at the same time so that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple, elegant
solution.
I was just wondering if anyone had done anything similar before... if not, I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

 

[Jim Granville]

Tom Derham wrote:

I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to the
other boards, to allow them to synchronise internal timers. I need to make
sure that the pulse arrives at the other two boards at the same time so that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple, elegant
solution.
I was just wondering if anyone had done anything similar before... if not, I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

The natsemi drivers might seem an over-kill, but they do give you
tracking with your clock system, and since that sounds like
it rather matters, anything you
a) already know
and
b) tracks what you already use

sounds to me like a simple, elegant solution ?

Another scheme for global sync, (but that some systems cannot
tolerate), is to send a break in the clock stream - can be as simple as
a single missing pulse. Gives you a time-Zero, and all units thereafter
are in-phase.

-jg

 

[Rene Tschaggelar]

Tom Derham wrote:

I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to the
other boards, to allow them to synchronise internal timers. I need to make
sure that the pulse arrives at the other two boards at the same time so that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple, elegant
solution.
I was just wondering if anyone had done anything similar before... if not, I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

100 MHz on a long cable calls for either 50 Ohms, ECL or perhaps LVDS.

There also are the AnalogDevices ADum1400 family of magnetocouplers,
some of which are spec'ed for 100MBit.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Rajeev]

Rene Tschaggelar <none@none.net> wrote in message news:<40b32543$0$718$5402220f@news.sunrise.ch>...

100 MHz on a long cable calls for either 50 Ohms, ECL or perhaps LVDS.

There also are the AnalogDevices ADum1400 family of magnetocouplers,
some of which are spec'ed for 100MBit.

Rene

One more vote for LVDS. Here's an app note for TI M-LVDS technology.

http://focus.ti.com/lit/an/slla127/slla127.pdf

Basically they say -6dB at 30m over UTP for 100 Mbps, and a little
over 10% jitter at 50m. I expect you may be able to do better with
co-ax cable -- look for a type with low-loss dielectric and, for lower
power consumption, higher characteristic impedance -- co-ax goes upto
about 100ohm. You will need to
be careful about ground differences between the two ends.

Regards,
-rajeev-

 

[John_H]

How about this weird idea: Don't send a pulse, send an edge. Your
attenuation might provide a little phase shift but it would be pretty easy
to alter the phase to match the clocks. Rather than a smeared pulse with
low high-level amplitudes, you get a full transition with a consistent 50%
point.


"Tom Derham" <uceeted@ucl.ac.uk> wrote in message
news:xtvsc.1724$hu1.16883825@news-text.cableinet.net...

I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to
the
other boards, to allow them to synchronise internal timers. I need to
make
sure that the pulse arrives at the other two boards at the same time so
that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to
not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple,
elegant
solution.
I was just wondering if anyone had done anything similar before... if not,
I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference
in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

 

[Peter Alfke]

Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.
=====================================
John_H wrote:

How about this weird idea: Don't send a pulse, send an edge. Your
attenuation might provide a little phase shift but it would be pretty easy
to alter the phase to match the clocks. Rather than a smeared pulse with
low high-level amplitudes, you get a full transition with a consistent 50%
point.

"Tom Derham" <uceeted@ucl.ac.uk> wrote in message
news:xtvsc.1724$hu1.16883825@news-text.cableinet.net...
I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to
the
other boards, to allow them to synchronise internal timers. I need to
make
sure that the pulse arrives at the other two boards at the same time so
that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to
not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple,
elegant
solution.
I was just wondering if anyone had done anything similar before... if not,
I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference
in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

 

Peter Alfke <peter@xilinx.com> wrote in message news:<40B38A28.FDBF2E3F@xilinx.com>...

Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.

Great solution, Peter. Some years ago I used this scheme to
communicate two systems ... until I change to Manchester ;-).

Anyway, has someone thought that the signal needs about 250 ns (25
clock cycles at 100 MHz) to fly from one board to the others. 50m are
50m, and light speed is light speed.

 

[Gabor Szakacs]

To go one step further with Peter's idea, you can AC couple if instead
of sending an occasional "pulse" (one cycle of 70% high) you send a
"square wave" of say 50 cycles of 30% high followed by 50 cycles of 70%
high. This gives you synchronizing events at each edge of the wave and
keeps the DC balance over the period of 1uS.
Peter Alfke <peter@xilinx.com> wrote in message news:<40B38A28.FDBF2E3F@xilinx.com>...

Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.
=====================================
John_H wrote:

How about this weird idea: Don't send a pulse, send an edge. Your
attenuation might provide a little phase shift but it would be pretty easy
to alter the phase to match the clocks. Rather than a smeared pulse with
low high-level amplitudes, you get a full transition with a consistent 50%
point.

"Tom Derham" <uceeted@ucl.ac.uk> wrote in message
news:xtvsc.1724$hu1.16883825@news-text.cableinet.net...
I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to
the
other boards, to allow them to synchronise internal timers. I need to
make
sure that the pulse arrives at the other two boards at the same time so
that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to
not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple,
elegant
solution.
I was just wondering if anyone had done anything similar before... if not,
I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference
in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

 

[Rene Tschaggelar]

sanpab@eis.uva.es wrote:

Peter Alfke <peter@xilinx.com> wrote in message news:<40B38A28.FDBF2E3F@xilinx.com>...

Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.


Great solution, Peter. Some years ago I used this scheme to
communicate two systems ... until I change to Manchester ;-).

Anyway, has someone thought that the signal needs about 250 ns (25
clock cycles at 100 MHz) to fly from one board to the others. 50m are
50m, and light speed is light speed.

And you want us to give you a link to a cheap, or better
to a free time machine ?

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Jim Granville]

sanpab@eis.uva.es wrote:

Peter Alfke <peter@xilinx.com> wrote in message news:<40B38A28.FDBF2E3F@xilinx.com>...

Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.


Great solution, Peter. Some years ago I used this scheme to
communicate two systems ... until I change to Manchester ;-).

Anyway, has someone thought that the signal needs about 250 ns (25
clock cycles at 100 MHz) to fly from one board to the others. 50m are
50m, and light speed is light speed.

Yes, but the OP did say the cable lengths were equal ?


Gabor Szakacs wrote:

To go one step further with Peter's idea, you can AC couple if instead
of sending an occasional "pulse" (one cycle of 70% high) you send a
"square wave" of say 50 cycles of 30% high followed by 50 cycles of 70%
high. This gives you synchronizing events at each edge of the wave and
keeps the DC balance over the period of 1uS.

This is how TV frame sync pulses are sent, and is a good idea.
-jg

 

[Peter Alfke]

That's a lot of wasted overhead time, and I threw in the warning about
the need for dc coupling as a afterthought. Why would anybody use ac coupling?

Regarding the train of 25 to 30 pulses travelling together on the
cable: That's fine, if you terminated the far end properly !

Peter Alfke
===============
Gabor Szakacs wrote:

To go one step further with Peter's idea, you can AC couple if instead
of sending an occasional "pulse" (one cycle of 70% high) you send a
"square wave" of say 50 cycles of 30% high followed by 50 cycles of 70%
high. This gives you synchronizing events at each edge of the wave and
keeps the DC balance over the period of 1uS.
Peter Alfke <peter@xilinx.com> wrote in message news:<40B38A28.FDBF2E3F@xilinx.com>...
Here is another suggestion:
Normally transmit a clock that is 30% High, 70% Low, but at the
synchronization moment, change one time to 70% High, 30%Low.
In the receiver, use the DLL to generate 50% duty cycle (the DLL is
always triggered on the rising clock edge). Then use the falling output
edge from the DLL to clock the incoming clock level into a flip-flop.
This flip-flop will be High for just one clock cycle.
This idea is similar to the "missing clock pulse synchronization"
mentioned before, but avoids its problems...
BTW: You must dc-couple the clock for this suggestion !
Peter Alfke, Xilinx Applications.
=====================================
John_H wrote:

How about this weird idea: Don't send a pulse, send an edge. Your
attenuation might provide a little phase shift but it would be pretty easy
to alter the phase to match the clocks. Rather than a smeared pulse with
low high-level amplitudes, you get a full transition with a consistent 50%
point.

"Tom Derham" <uceeted@ucl.ac.uk> wrote in message
news:xtvsc.1724$hu1.16883825@news-text.cableinet.net...
I am using 3 Xilinx SpartanIIE boards, each loaded with a similar design
running with a 100MHz master clock. This clock is derived from a single
source and distributed to each board so they are synchronised. The boards
are postioned about 50m apart.

I need to synchronise events on the boards, but occasionally sending a
single pulse (say 10ns long) from the output pin of one of the FPGAs to
the
other boards, to allow them to synchronise internal timers. I need to
make
sure that the pulse arrives at the other two boards at the same time so
that
it is 'recognised' on the same rising edge of the reference clock in each
case, so that the boards synchronise together.

Clearly the attenuation of any 50m length of cable is such that I cannot
connect them directly, but nor do I want the complexity of converting the
pulse to optical fibre and back again.
For the distribution of the reference clock I am using National CLC005/012
driver and equaliser chipset over UTP, using equal length wires so as to
not
introduce propagation skew. For practical reasons I can't use the same
cable for sending this event pulse, and ideally would like a simple,
elegant
solution.
I was just wondering if anyone had done anything similar before... if not,
I
have a back-up plan using more of the National drivers, but I thought they
might be a sledgehammer to crack a nut - and am unsure what levels of skew
they may introduce themselves... jitter is not so important because the
event is resynced at the receiving fpga, as long as the total difference
in
edge is less than half of the reference clock cycle (so 5ns).

Thank you in advance for any ideas....

 

[Jim Granville]

Peter Alfke wrote:

That's a lot of wasted overhead time, and I threw in the warning about
the need for dc coupling as a afterthought. Why would anybody use ac coupling?

Regarding the train of 25 to 30 pulses travelling together on the
cable: That's fine, if you terminated the far end properly !

ac coupling could allow improved ground tolerance ?.
The 50m is pushing LVDS common mode a little.

ac coupling would have minor effects, if the rolloff was right.
- a handfull of skewed clocks would pass OK.
What COULD be important, is the general LPF actions of longish
cables, and the eye distortions that causes.
Perhaps merit in a couplet of 30/70/70/30 as a minimal disturbance
sync scheme ( no nett low frequency content) ?
Because it uses a common clock, and can define a start edge
explicitly, this sync-on-clock scheme can deliver an order of
magnitude improvement over the OPs first jitter target, so it
pays to think just how good it can get.

-jg

 

[Tom Derham]

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:APwtc.4324$FN.454262@news02.tsnz.net...

ac coupling would have minor effects, if the rolloff was right.
- a handfull of skewed clocks would pass OK.
What COULD be important, is the general LPF actions of longish
cables, and the eye distortions that causes.
Perhaps merit in a couplet of 30/70/70/30 as a minimal disturbance
sync scheme ( no nett low frequency content) ?
Because it uses a common clock, and can define a start edge
explicitly, this sync-on-clock scheme can deliver an order of
magnitude improvement over the OPs first jitter target, so it
pays to think just how good it can get.

Some great thoughts and information, thank you!

Unfortunately I don't have much control over the master clock - it is
derived from an OCXO, goes through a power splitter, then is sent down the
cables using the Natsemi chipset (provides active equalisation at the
receiver based on high frequency content from which it can approximate the
cable length and hence the equalisation curve required). This clock must be
as low phase noise as possible because it is also used to clock other
components (e.g. ADC), and a clock derived from an FPGA (over which I could
have control) would have much worse jitter.

I like the idea of level sensing rather than edge sensing as the events are
only occasional - it just means that the threshold crossing should be stable
and occur during the same clock cycle at each board.
To that end, the TI M-LVDS chips look a good bet - high drive level, low
impedance.
They do however specify a ground voltage difference of less than 1V.
I can connect the grounds of the power supplies for each board together so
that should provide a fairly low impedance path.. I will try it out and
report back to the group.

Many thanks for your help
Tom

 

[Adrian]

test

Tom Derham wrote:

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:APwtc.4324$FN.454262@news02.tsnz.net...

ac coupling would have minor effects, if the rolloff was right.
- a handfull of skewed clocks would pass OK.
What COULD be important, is the general LPF actions of longish
cables, and the eye distortions that causes.
Perhaps merit in a couplet of 30/70/70/30 as a minimal disturbance
sync scheme ( no nett low frequency content) ?
Because it uses a common clock, and can define a start edge
explicitly, this sync-on-clock scheme can deliver an order of
magnitude improvement over the OPs first jitter target, so it
pays to think just how good it can get.


Some great thoughts and information, thank you!

Unfortunately I don't have much control over the master clock - it is
derived from an OCXO, goes through a power splitter, then is sent down the
cables using the Natsemi chipset (provides active equalisation at the
receiver based on high frequency content from which it can approximate the
cable length and hence the equalisation curve required). This clock must be
as low phase noise as possible because it is also used to clock other
components (e.g. ADC), and a clock derived from an FPGA (over which I could
have control) would have much worse jitter.

I like the idea of level sensing rather than edge sensing as the events are
only occasional - it just means that the threshold crossing should be stable
and occur during the same clock cycle at each board.
To that end, the TI M-LVDS chips look a good bet - high drive level, low
impedance.
They do however specify a ground voltage difference of less than 1V.
I can connect the grounds of the power supplies for each board together so
that should provide a fairly low impedance path.. I will try it out and
report back to the group.

Many thanks for your help
Tom