M
MM
Guest
Hi experts,
I am looking at the code example on Fig. 7.2.6-2 in VHDL Coding Styles and
Methodologies by Ben Cohen and struggling to understand what the Data_s is
supposed to look like? Are those waits in the procedure supposed to do
something? I have simulated it and they seem to be doing nothing... The
data changes only on clock...
Thanks,
/Mikhail
I am looking at the code example on Fig. 7.2.6-2 in VHDL Coding Styles and
Methodologies by Ben Cohen and struggling to understand what the Data_s is
supposed to look like? Are those waits in the procedure supposed to do
something? I have simulated it and they seem to be doing nothing... The
data changes only on clock...
Thanks,
/Mikhail