DRC in Virtuoso????

L

Lee

Guest
Hello,

If one standard cell library doesn't have layout view but it has
abstract view, can I make DRC for routed wire without standard cell
after placement&router?

I tried the hierachy method (i.e. the top design includes the routed
wire and abstract view of standard cell instances), but it seems not
working. Can you give me some hints?

A million thanks,

Adrian
 
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
Andrew,

This solution definitely works. Thanks.

One more question. If I do DRC in this way, how can I extract
parasistics for post-layout simulation?

I am thinking one way: extract the wire parasistics and replace
wireload models in Synopsys by annotating the parasistics to the
design in Synopsys.Is it right?Or better way exist?

Best regards,


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<uep0h05bfca3l2jrtjikpkfmc2h2egga73@4ax.com>...
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.
Click to expand...
 
While Andrew's solution does work, it does not check for problems
between the routing and the cell content. Every layer in the abstract
view should have keepout shapes that represent the area occupied by the
internal shapes without actually being those shapes. This lets you check
for DRC violations between the cell and the routing.

As for parasitics, you can have the abstract view switch to a schematic
or symbol view during netlisting for the simulator. Assuming the
schematic or symbol have the appropriate information, the simulator
should have everything it needs without any annotation on your part.

On 4 Aug 2004 12:58:30 -0700, yxl4444@louisiana.edu (Lee) wrote:

Andrew,

This solution definitely works. Thanks.

One more question. If I do DRC in this way, how can I extract
parasistics for post-layout simulation?

I am thinking one way: extract the wire parasistics and replace
wireload models in Synopsys by annotating the parasistics to the
design in Synopsys.Is it right?Or better way exist?

Best regards,


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<uep0h05bfca3l2jrtjikpkfmc2h2egga73@4ax.com>...
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.
Click to expand...
 
Hi,

Thanks for your answer.

More questions,

How can I check for problems between the routing and the cell content
without layout view?

How can I extract the wire parasitics only?

You know, the current library I am using doesn't have the layout view.
I want to make sure everything is OK before I pay money to the library
vendor and get the layout view and simulate the design again. What is
the best design flow?

Best regards,

Diva Physical Verification <diva@cadence.com> wrote in message news:<frg2h0hagku075c9hb7dsbb73dgtr1q6ho@4ax.com>...
While Andrew's solution does work, it does not check for problems
between the routing and the cell content. Every layer in the abstract
view should have keepout shapes that represent the area occupied by the
internal shapes without actually being those shapes. This lets you check
for DRC violations between the cell and the routing.

As for parasitics, you can have the abstract view switch to a schematic
or symbol view during netlisting for the simulator. Assuming the
schematic or symbol have the appropriate information, the simulator
should have everything it needs without any annotation on your part.

On 4 Aug 2004 12:58:30 -0700, yxl4444@louisiana.edu (Lee) wrote:

Andrew,

This solution definitely works. Thanks.

One more question. If I do DRC in this way, how can I extract
parasistics for post-layout simulation?

I am thinking one way: extract the wire parasistics and replace
wireload models in Synopsys by annotating the parasistics to the
design in Synopsys.Is it right?Or better way exist?

Best regards,


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<uep0h05bfca3l2jrtjikpkfmc2h2egga73@4ax.com>...
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.
Click to expand...
 
You check for errors using the abstract view, as I said. A properly
built abstract can be used for that purpose. You do not need the layout
to check for routing to cell problems.

On 5 Aug 2004 07:25:25 -0700, yxl4444@louisiana.edu (Lee) wrote:

Hi,

Thanks for your answer.

More questions,

How can I check for problems between the routing and the cell content
without layout view?

How can I extract the wire parasitics only?

You know, the current library I am using doesn't have the layout view.
I want to make sure everything is OK before I pay money to the library
vendor and get the layout view and simulate the design again. What is
the best design flow?

Best regards,

Diva Physical Verification <diva@cadence.com> wrote in message news:<frg2h0hagku075c9hb7dsbb73dgtr1q6ho@4ax.com>...
While Andrew's solution does work, it does not check for problems
between the routing and the cell content. Every layer in the abstract
view should have keepout shapes that represent the area occupied by the
internal shapes without actually being those shapes. This lets you check
for DRC violations between the cell and the routing.

As for parasitics, you can have the abstract view switch to a schematic
or symbol view during netlisting for the simulator. Assuming the
schematic or symbol have the appropriate information, the simulator
should have everything it needs without any annotation on your part.

On 4 Aug 2004 12:58:30 -0700, yxl4444@louisiana.edu (Lee) wrote:

Andrew,

This solution definitely works. Thanks.

One more question. If I do DRC in this way, how can I extract
parasistics for post-layout simulation?

I am thinking one way: extract the wire parasistics and replace
wireload models in Synopsys by annotating the parasistics to the
design in Synopsys.Is it right?Or better way exist?

Best regards,


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<uep0h05bfca3l2jrtjikpkfmc2h2egga73@4ax.com>...
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.
Click to expand...
 
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