DRC for large chips

[Kuan Zhou]

Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department

 

[Bernd Fischer]

You don't let us know with which tool you are doing DRC

there are a bunch of DRC tools on the market Cadence and non Cadence
one.

I assume you use Cadence Diva which may possible not has the capacity to
do DCR on a real big Chip.

Also not the chip size is the important factor on defining if a chip is
big for a DRC tool, it more the chip size in relation to the technology
e.g. 0.13um 0.18um or 0.25um etc.. Which really makes a difference in
shapes are used on the chip.

Bernd

Kuan Zhou wrote:

Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department

 

[Kuan Zhou]

Hi,
I am using 0.13 technology. Also I am using Diva for DRC.
Can you give me any suggestions how to finish the DRC?

sincerely
-------------
Kuan Zhou
ECSE department


On Thu, 8 Jul 2004, Bernd Fischer wrote:

You don't let us know with which tool you are doing DRC

there are a bunch of DRC tools on the market Cadence and non Cadence
one.

I assume you use Cadence Diva which may possible not has the capacity to
do DCR on a real big Chip.

Also not the chip size is the important factor on defining if a chip is
big for a DRC tool, it more the chip size in relation to the technology
e.g. 0.13um 0.18um or 0.25um etc.. Which really makes a difference in
shapes are used on the chip.

Bernd

Kuan Zhou wrote:
Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department

 

[Richard Griffith]

Kuan Zhou wrote:

Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

From Cadence you can use Assura. From Mentor you can use Calibre. Both
are good on large designs and support hierarchical operation. Also both
support operation on GDSII data bases, something I like much better than
operating on the "live" database as Diva does.

The big question is can you use your existing DRC deck which I presume
you have from the foundry. The foundry may directly support the
alternative tool. I believe both Assura and Mentor support translation
of Diva files. These may not be 100% nor the most efficient solutions.

 

[Raf]

Hi,

If your design is repetitive (memory cells for example), you can use
hierarchical DRC tools which greatly speed up the DRC.

Raf


Kuan Zhou wrote:

Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department

 

[Kuan Zhou]

Hi,
when I use diva for DRC, I used the hierarchial DRC. But it has a
error message called: Too many layers for DRC. Does anyone know how to
solve it?

sincerely
-------------
Kuan Zhou
ECSE department


On Fri, 9 Jul 2004, Raf wrote:

Hi,

If your design is repetitive (memory cells for example), you can use
hierarchical DRC tools which greatly speed up the DRC.

Raf


Kuan Zhou wrote:
Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department

 

[Diva Physical Verificatio]

Hierarchical DRC has a limit to the number of graphic layers that can be
referred to by the rule deck. Too bizarre and complicated to explain in
any useful detail. It is enough to say that only 64 graphic layers can
be used in the rule deck. I know of no reason this cannot be increased,
but it would have to be a code change. There is no way for the user to
do it. File a P0 bug report. They usually get very quick fixes from Diva
R&D.

As a general note, hierarchical DRC in Diva is not as robust a tool as
Assura or the others. If your cells have errors which are corrected in a
parent cell, there is no provision for removal of the error markers in
the child cell. Of course, if each cell is DRC clean, this is not a
problem.

In general, if you want to use hierarchical DRC in Diva, I usually
recommend that you design your rule deck with careful attention to the
section on HDRC in the manual and that you constrain your design style
to be:
1) Every cell is DRC clean.
2) No cell instance overlaps another cell instance.
3) No shape overlaps a cell instance.

On Thu, 8 Jul 2004 23:02:13 -0400, Kuan Zhou <zhouk@rpi.edu> wrote:

Hi,
when I use diva for DRC, I used the hierarchial DRC. But it has a
error message called: Too many layers for DRC. Does anyone know how to
solve it?

sincerely
-------------
Kuan Zhou
ECSE department


On Fri, 9 Jul 2004, Raf wrote:

Hi,

If your design is repetitive (memory cells for example), you can use
hierarchical DRC tools which greatly speed up the DRC.

Raf


Kuan Zhou wrote:
Hi,
we have encountered a big problem of DRC. We have designed a 1cm x 7mm
chip. However, when we do DRC check for this chip, Cadence keeps crashing.
Does anyone know a better way to do DRC? We are running IC 5.0.33 on
slackware and Solaris 8.

Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department