DRC/EXTRACT/LVS memory

[Arnold]

Hi,

I am using Diva as checking tool for DRC and LVS.
Do someone know, how many memory (RAM) is necessary
for a specific size of a design ?
I have the problem, that the EXTRACT/LVS does not finish,
and we get the message that cadence need more memory.
(sometimes only 10 to 200 Bytes more)
Our workstation has now 8 GByte of RAM, and it is still
not enough.
THX

Arnold

 

[John Gianni]

In addition, for what it's worth, the Cadence system configuration
checker (checkSysConfig) shipped with every release of every tool at
Cadence for the past few years tells you the MINIMUM memory required to
run the tool.

I fought for years to get this tool to Customers and I'm glad it is now
available to Customers ... however ... bluntly stated, while it does
patch levels rather well, it doesn't do a whole lot for memory and swap
needs.

Still, it's something you should run BEFORE you run Diva (or any
Cadence tool).

You can pick up the latest checkSysConf Cadence System Configuration
Checker on Sourcelink.

John Gianni
--
Absolutely nothing I say on the USENET is sanctioned by my employer.

 

[Diva Physical Verificatio]

Ignore the amount it tells you it needs. That's the memory allocater
telling you how big an allocation it was just asked for. Completely
meaningless information.

Information, please. Which is not finishing? Extract or LVS? They are
different binaries. Different steps in the flow. How many devices does
your design have in it? What version are you running? What OS?

In general, DRC and Extract use very little memory, except during the
geomConnect rule. I've run 500K device designs on my 1 gig UltraSparcII.
What is your VM size before you start the Extract? That's how much
memory the database and graphic editor are using, which may not leave
Diva much to work in. Flatten the 500K device design and there is not
much left.

LVS can be very memory intensive. The memory usage starts proportional
to the number of nets, devices, device pins and device property
characters. Then the logic combination process starts making meta
devices. The meta devices take space, as does the undo information
needed for error reporting from the meta devices. This makes it hard to
predict memory usage of LVS. If your circuit combines into logic
functions really well, it can double or triple the memory usage.

Both DRC/Extract and LVS can run in 64bit mode to take advantage of the
extra RAM. I would monitor the run using the top utility to see how much
VM the process is using when it fails. Some workstations have small VM
quotas for some reason only IT seems able to understand.

As always, I'll be happy to see a bug report come in for any Diva
problem. Just submit everything, through your FAE, needed to reproduce
the problem. We can work on problems like this blind, but who knows if
it will fix *your* particular problem.

On 13 Jan 2005 03:03:24 -0800, arnold_erni@yahoo.de (Arnold) wrote:

Hi,

I am using Diva as checking tool for DRC and LVS.
Do someone know, how many memory (RAM) is necessary
for a specific size of a design ?
I have the problem, that the EXTRACT/LVS does not finish,
and we get the message that cadence need more memory.
(sometimes only 10 to 200 Bytes more)
Our workstation has now 8 GByte of RAM, and it is still
not enough.
THX

Arnold