R
renee
Guest
Dear all,
I drew the layout myself, and labels are on the pin layer.
When I run DRC check, it said that "Label/Pin is on a net with a
different name". But it is strange that the first time I run, it said
Label/Pin "gnd!" is on a net already named "Y", but the next day, I
run , then it said "Label/Pin "Y" is on a net already named "gnd!"". I
did not change the layout between two DRC check. The switch names I
used are "drc_shape? not_pads?".
Actually, at first I did not find some logic errors on the
layout, and then I run extract and LVS. Later I found the error, and
went back to change the layout and do drc. The Label/Pin errors then
came up.
Is it the reason why it said "label/pin is on a net with a
different name"?
Thank you very much!
Renee
I drew the layout myself, and labels are on the pin layer.
When I run DRC check, it said that "Label/Pin is on a net with a
different name". But it is strange that the first time I run, it said
Label/Pin "gnd!" is on a net already named "Y", but the next day, I
run , then it said "Label/Pin "Y" is on a net already named "gnd!"". I
did not change the layout between two DRC check. The switch names I
used are "drc_shape? not_pads?".
Actually, at first I did not find some logic errors on the
layout, and then I run extract and LVS. Later I found the error, and
went back to change the layout and do drc. The Label/Pin errors then
came up.
Is it the reason why it said "label/pin is on a net with a
different name"?
Thank you very much!
Renee