DPRAM using the CoreGenerator, VHDL-example

  • Thread starter Tobias Möglich
  • Start date
T

Tobias Möglich

Guest
Hello,
I'm using Xilinx ISE 6.1.
I'm using the CoreGenerator for designing a dual port RAM (block RAM).
Is there an example in VHDL how to access the RAM and read the RAM?
How can I say ISE to use the generated core and not for example
distributed single port RAM or what ever he want's?

And since I use the CoreGenerator I can say how wide port A and how wide
port B should be. (I.e : port A: 8 bit; port B: 16 bit).
ISE doesn't know at all (I suppose) that I want to use my generated core
where I already defined the width of port A and port B.
He criticizes it .

Can someone help me?

Tobias Möglich
 
When you generate a module with CoreGen, you should instantiate it(not infer
it) in your code to tell the ISE you want to use it.

"Tobias Möglich" <Tobias.Moeglich@gmx.net>
??????:3FFC4BC2.F86BCF11@gmx.net...
Hello,
I'm using Xilinx ISE 6.1.
I'm using the CoreGenerator for designing a dual port RAM (block RAM).
Is there an example in VHDL how to access the RAM and read the RAM?
How can I say ISE to use the generated core and not for example
distributed single port RAM or what ever he want's?

And since I use the CoreGenerator I can say how wide port A and how wide
port B should be. (I.e : port A: 8 bit; port B: 16 bit).
ISE doesn't know at all (I suppose) that I want to use my generated core
where I already defined the width of port A and port B.
He criticizes it .

Can someone help me?

Tobias Möglich
Click to expand...
 
What does this mean in detail ???

Tobias



Jay wrote:

When you generate a module with CoreGen, you should instantiate it(not infer
it) in your code to tell the ISE you want to use it.

"Tobias Möglich" <Tobias.Moeglich@gmx.net
??????:3FFC4BC2.F86BCF11@gmx.net...
Hello,
I'm using Xilinx ISE 6.1.
I'm using the CoreGenerator for designing a dual port RAM (block RAM).
Is there an example in VHDL how to access the RAM and read the RAM?
How can I say ISE to use the generated core and not for example
distributed single port RAM or what ever he want's?

And since I use the CoreGenerator I can say how wide port A and how wide
port B should be. (I.e : port A: 8 bit; port B: 16 bit).
ISE doesn't know at all (I suppose) that I want to use my generated core
where I already defined the width of port A and port B.
He criticizes it .

Can someone help me?

Tobias Möglich
Click to expand...
 
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