DPRAM design issue

[ian]

hi, Folks,
I have a dual port RAM with the same width at both side, which is
32bit. However, the data in at A side is only 16 bit wide. So in order
to pass the data in and fill the RAM entry, i need to use some wrapper
logic (mux?) to pass data in to fill the upper and lower 16 bits in
one address of the DRAM in two consequtive clock cycles. Therefore as
issue of testablity arises, since the mux logic is not insertable in
terms of scan flops. also I have to introduce a clock cycle latency
into the A side to fill up the 32 bit entry. Are there any nice
tricks to avoid both of the problems? (of course without changing the
DPRAM.)
Thanks in advance

Ian

 

[Peter Alfke]

The easiest trick would be to use the Xilinx BlockRAM, where that whole
problem is solved for you.
Sorry for the commercial, but you gave no restrictions in RAM size....
Peter Alfke

ian wrote:

hi, Folks,
I have a dual port RAM with the same width at both side, which is
32bit. However, the data in at A side is only 16 bit wide. So in order
to pass the data in and fill the RAM entry, i need to use some wrapper
logic (mux?) to pass data in to fill the upper and lower 16 bits in
one address of the DRAM in two consequtive clock cycles. Therefore as
issue of testablity arises, since the mux logic is not insertable in
terms of scan flops. also I have to introduce a clock cycle latency
into the A side to fill up the 32 bit entry. Are there any nice
tricks to avoid both of the problems? (of course without changing the
DPRAM.)
Thanks in advance

Ian