DPLL in FPGA ?? (Xilinx)

[5hinka]

Anybody have any schematics or programs (VHDL/Verilog)
of DPLL for FPGAs ?? Where could i find such "knowledge" ??
Thx
5hinka

 

[Mike Randelzhofer]

"5hinka" <anonim99@poczta.wp.pl> schrieb im Newsbeitrag
news:c48u0d$307$1@nemesis.news.tpi.pl...

Anybody have any schematics or programs (VHDL/Verilog)
of DPLL for FPGAs ?? Where could i find such "knowledge" ??
Thx
5hinka

This question should be asked in comp.arch.fpga.
Please add your precise requirements as the description of your application,
input and output clock, and jitter.

MIKE

 

[Tim Wescott]

Mike Randelzhofer wrote:

"5hinka" <anonim99@poczta.wp.pl> schrieb im Newsbeitrag
news:c48u0d$307$1@nemesis.news.tpi.pl...

Anybody have any schematics or programs (VHDL/Verilog)
of DPLL for FPGAs ?? Where could i find such "knowledge" ??
Thx
5hinka


This question should be asked in comp.arch.fpga.
Please add your precise requirements as the description of your application,
input and output clock, and jitter.

MIKE

And check the Xilinx website -- those people thrive on this sort of
stuff. Xilinx is currently pushing their "DLL" (delay locked loop) for
messing with clocks, so they may not have as much as you want, but look.

---------------------------------------
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Frank Raffaeli]

"5hinka" <anonim99@poczta.wp.pl> wrote in message news:<c48u0d$307$1@nemesis.news.tpi.pl>...

Anybody have any schematics or programs (VHDL/Verilog)
of DPLL for FPGAs ?? Where could i find such "knowledge" ??
Thx
5hinka

I have implemented close to a dozen digital PLL's in Altera, some in
VHDL. Some of these may port easily to Xilinx. I might have one or two
close to your application, but as far as I know, there is no "Generic"
solution.

The DPLL applications I am familiar with usually relate to
demodulation. If you are looking for an FPGA clock multiplier
(sometimes called DPLL), then there are built-in options for most of
the FPGA varieties.

What is your application?

Frank Raffaeli
http://www.aomwireless.com/

 

[Markus Meng]

Hi,

I don't know how fine the resolution for the jitter measurment
shall be, however maybe you should NOT use the internal DLL (DCM)
ot the Xilinx parts, because these clock management subsystem do
generate some additional jitter ... normally you can not drive
the clock for SONET or SERDES devices through a DLL ... cause of
jitter constraints ...

markus

"5hinka" <anonim99@poczta.wp.pl> wrote in message news:<c4bp64$3s6$1@atlantis.news.tpi.pl>...

I have implemented close to a dozen digital PLL's in Altera, some in
VHDL. Some of these may port easily to Xilinx. I might have one or two
close to your application, but as far as I know, there is no "Generic"
solution.

The DPLL applications I am familiar with usually relate to
demodulation. If you are looking for an FPGA clock multiplier
(sometimes called DPLL), then there are built-in options for most of
the FPGA varieties.

What is your application?


Hole aplication is a jitter measurer for 2Mbit (HDB3). But DPLL will
have on input signal - clock recovered from HDB3 signal with jitter
and should eliminate this jitter in different time periods. (Time periods
will be chosen by me for checking all ITU-T regulations). So output signal
from DPLL will be 2Mbit signal without any jitter (as low as possible).

Greetings
5hinka
ps Sorry for my English - I hope it is understandable.

 

[Martin Riddle]

True, the DLL is based on a vco.

Cheers

"Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:aaaee51b.0403301213.4b7c11ec@posting.google.com...

Hi,

I don't know how fine the resolution for the jitter measurment
shall be, however maybe you should NOT use the internal DLL (DCM)
ot the Xilinx parts, because these clock management subsystem do
generate some additional jitter ... normally you can not drive
the clock for SONET or SERDES devices through a DLL ... cause of
jitter constraints ...

markus

"5hinka" <anonim99@poczta.wp.pl> wrote in message news:<c4bp64$3s6$1@atlantis.news.tpi.pl>...

I have implemented close to a dozen digital PLL's in Altera, some in
VHDL. Some of these may port easily to Xilinx. I might have one or two
close to your application, but as far as I know, there is no "Generic"
solution.

The DPLL applications I am familiar with usually relate to
demodulation. If you are looking for an FPGA clock multiplier
(sometimes called DPLL), then there are built-in options for most of
the FPGA varieties.

What is your application?


Hole aplication is a jitter measurer for 2Mbit (HDB3). But DPLL will
have on input signal - clock recovered from HDB3 signal with jitter
and should eliminate this jitter in different time periods. (Time periods
will be chosen by me for checking all ITU-T regulations). So output signal
from DPLL will be 2Mbit signal without any jitter (as low as possible).

Greetings
5hinka
ps Sorry for my English - I hope it is understandable.