DPLL in CPLD

[Jim]

Hi all,

i need to implement a (D) PLL in a CPLD.

Purpose is to multiply a frequency of 32KHz to 4,096KHz.
On board PLL's don't work since the freq. is very low

How do i start?

Jim

 

[Jim Granville]

Jim wrote:

Hi all,

i need to implement a (D) PLL in a CPLD.

Purpose is to multiply a frequency of 32KHz to 4,096KHz.
On board PLL's don't work since the freq. is very low

How do i start?

DPLLs ( digital phase locked loops ) have phase jitter, so first
step is to decide how much phase jitter you can tolerate @ 4MHz.
To keep jitter reasonable, DPLLs need a time granularity well
above the reqired Freq out, so you need a faster clock.
You may decide an Analog PLL like a HC4046, with the divide in CPLD
gives better performance.
-jg

 

[Leon Heller]

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:RTHCc.4326$NA1.419961@news02.tsnz.net...

Jim wrote:

Hi all,

i need to implement a (D) PLL in a CPLD.

Purpose is to multiply a frequency of 32KHz to 4,096KHz.
On board PLL's don't work since the freq. is very low

How do i start?

DPLLs ( digital phase locked loops ) have phase jitter, so first
step is to decide how much phase jitter you can tolerate @ 4MHz.
To keep jitter reasonable, DPLLs need a time granularity well
above the reqired Freq out, so you need a faster clock.
You may decide an Analog PLL like a HC4046, with the divide in CPLD
gives better performance.

The phase detector could also be implemented in the CPLD, leaving just the
VCO.

Leon
--
Leon Heller, G1HSM
http://www.geocities.com/leon_heller

 

[Jim]

Jim Granville <no.spam@designtools.co.nz> schreef in berichtnieuws
RTHCc.4326$NA1.419961@news02.tsnz.net...

Jim wrote:

Hi all,

i need to implement a (D) PLL in a CPLD.

Purpose is to multiply a frequency of 32KHz to 4,096KHz.
On board PLL's don't work since the freq. is very low

How do i start?

DPLLs ( digital phase locked loops ) have phase jitter, so first
step is to decide how much phase jitter you can tolerate @ 4MHz.
To keep jitter reasonable, DPLLs need a time granularity well
above the reqired Freq out, so you need a faster clock.
You may decide an Analog PLL like a HC4046, with the divide in CPLD
gives better performance.
-jg

Thanks Jim, but your suggestion is how it's done right now, the counter
resides in the CPLD.
my goal was/is to get rid of the 4046, and some r/c's.
since we're using a CPLD, why not create an 'all in one'approach?

Regards,
Jim

 

[Hal Murray]

Thanks Jim, but your suggestion is how it's done right now, the counter
resides in the CPLD.
my goal was/is to get rid of the 4046, and some r/c's.
since we're using a CPLD, why not create an 'all in one'approach?

The basic idea is that it's hard to make a faster clock
with digital logic. Especially clean logic.

You can make a slower clock. For example if you have 1 MHz, you
can get 1 KHz by dividing by 1000. You can lock the 1 KHz to a
reference clock by dividing by 1001 or 999 on as many of the
1 KHz cycles as needed to make it match. The jitter in your
output clock will be 1 cycle of your main clock.

The external 4046 has a VCO in it. That's what you need to
get the faster clock. The Rs and Cs are just a filter on the
VCO control voltage. You probably can't get rid of them.

You can do tricks with tapped delay lines. Read the Xilinx
data sheets (or the archives for this list) on their DLLs.
The numbers aren't good for building your own in a CPLD. You
need enough gates so that their total delay is your cycle time.
(You can go around several times, but that's the general time
scale.) Then you need switching logic to select between N and
N+1 or N-1 gates. The individual gate delay will be your
clock jitter.

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[Jim Granville]

Jim wrote:

Jim Granville <no.spam@designtools.co.nz> schreef in berichtnieuws
snip
DPLLs ( digital phase locked loops ) have phase jitter, so first
step is to decide how much phase jitter you can tolerate @ 4MHz.
To keep jitter reasonable, DPLLs need a time granularity well
above the reqired Freq out, so you need a faster clock.
You may decide an Analog PLL like a HC4046, with the divide in CPLD
gives better performance.
-jg



Thanks Jim, but your suggestion is how it's done right now, the counter
resides in the CPLD.
my goal was/is to get rid of the 4046, and some r/c's.
since we're using a CPLD, why not create an 'all in one'approach?

To replace the 4046, look at the individual blocks of the 4046:
The XOR phase comp, you can replace easily.
The tri-state charge pump phase comparitor is harder, but you
could probably get something with relaxed performance.
The VCO is A cross coupled latch, with open drain outputs, and
current sources.
Current sources do not exist in CPLD, but you could make the
OSC block, and use external sources.
You will always need some RCs in an analog VCO/PLL.

An alternative would be an LC osc, and a varicap diode, using
some tiny logic - but you are still in the specialised extra
parts domain.
I have not seen a tiny-logic 4046, but that would be a good product.

-jg