DOWNTO versus TO keyword on Component instantiation

Hello,

Does anyone know about the following error in Modelsim ?

** Error: xxx.vhd(2435): (vcom-1012) Slice range direction (to) does
not match slice prefix dire
ction (downto).

The slice range direction on the concerned port are identical on the
entity and on the component declaration (DOWNTO keyword) but I cant
use slice range direction (TO) in the assigned signal.
If I set TO every where is does not work better. The only solution is
using "downto" everywhere...

Is it a VHDL restriction ?

Thanks..

 

[Jonathan Bromley]

On Tue, 18 Nov 2008 02:59:51 -0800 (PST), pierre0102@gmail.com wrote:

Hello,

Does anyone know about the following error in Modelsim ?

** Error: xxx.vhd(2435): (vcom-1012) Slice range direction (to) does
not match slice prefix dire
ction (downto).

The slice range direction on the concerned port are identical on the
entity and on the component declaration (DOWNTO keyword) but I cant
use slice range direction (TO) in the assigned signal.
If I set TO every where is does not work better. The only solution is
using "downto" everywhere...

It sounds as though you are looking (and hacking) in the
wrong place.

In VHDL, a "to" vector is copy-compatible (and, similarly,
port connection compatible) with a "downto" vector of
the same type and width. So, for example:

signal S: std_logic_vector(7 downto 0);
...
component C is
port (P: in std_logic_vector(1 to 8));
end component;
...
begin
instance: C port map (P => S); -- This is fine.

In that example, the connections are:

port P ...... 1 2 3 4 5 6 7 8
connects to : : : : : : : :
signal S .... 7 6 5 4 3 2 1 0

following the usual VHDL copy/connection rules about
strict left-to-right ordering of the elements.

What I suspect you have done is to try to connect a
slice of an existing signal to a port, like this:

signal S: std_logic_vector(7 downto 0); -- 8 bits
...
component C is
port (P: in std_logic_vector(3 downto 0)); -- 4 bits
end component;
...
begin
instance: C port map (P => S(0 to 3)); -- Error.

The problem here is nothing to do with the subscript
direction (to/downto) on the component; it is a mismatch
between the "downto" subscript range of S and the
slice (0 to 3). Make the slice direction match the signal's
declaration, like it says in the nice error message.
--
Jonathan Bromley, Consultant

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