Downloading to an FPGA

[Chris]

Hello,

I have an XILINX FPGA evaluation board with a JTAG pod, which connects to
the parallel port. To download my VHDL code I'm using the iMPACT software.
If I repeatably download code to the FPGA it starts to act in a strange way
e.g. parts of it just stop working. The only way I can overcome this is to
remove the power supply and then reattach it, therefore reseting it. After
doing this everything works fine.

Is this a common problem with FPGA's or am I doing something wrong? Could
it be a problem in my code or do I just have to keep toggling the power to
the FPGA?

Thanks for any advice,

 

[Steve Casselman]

I think only the Virtex II or Pro has a "reset device" command from JTAG.
You need to ground the prog pin or remove the power each time. The only
other way might be to make a "blank" design and load that before you load
your design. Just as a matter of jargon you download bitstreams that make
come from VHDL you don't download a VHDL file.

Steve


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"Chris" <Chris@nospam.com> wrote in message
news:buduhr$meb$1@news7.svr.pol.co.uk...

Hello,

I have an XILINX FPGA evaluation board with a JTAG pod, which connects to
the parallel port. To download my VHDL code I'm using the iMPACT
software.
If I repeatably download code to the FPGA it starts to act in a strange
way
e.g. parts of it just stop working. The only way I can overcome this is
to
remove the power supply and then reattach it, therefore reseting it.
After
doing this everything works fine.

Is this a common problem with FPGA's or am I doing something wrong? Could
it be a problem in my code or do I just have to keep toggling the power to
the FPGA?

Thanks for any advice,