Doulos training courses at Xilinx

M

Mr.CRC

Guest
Hi:

While I'm very able to learn on my own, I feel that at my age and with
so many people pulling at me every minute, that to assemble the hours of
focussed attention to actually work through a significant amount of
study material, these sorts of immersion courses are beneficial.

Of course, that also assumes that my employer is willing to pay for it,
which they are. If I had to pay, then the economics would be in favor
of cracking a book and taking the fully DIY approach--which is basically
how I've learned nearly everything I know about electronics to date.

Of course, these sorts of courses require a lot of DIY follow-through to
drive things home.

In this case, since I have quite a bit of increasingly complicated
(though still fairly simple by the standards of most experts) FPGA
development to do over the next few years, there will be ample
opportunity to exercise what I have learned.

I think the point is, that there are a lot of practices that aren't
obviated by simply reading a Verilog textbook. Even some of the "learn
by example" books have some shoddy practices.

Also, I suffer from "tool overwhelmitis" syndrome, where there are so
many sub-tools in the vendor's development environment that I don't know
what they are all for.


Anyway, I am considering to take the "Comprehensive Verilog" and
"Essentials and Design for Performance" classes by Doulos at Xilinx in Dec.

Just wondering if people think these are worthwhile?

Thanks for input. And output too. Just no high-z's!


Good day!


--
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17
 
"Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net> wrote:

Hi:

While I'm very able to learn on my own, I feel that at my age and with
so many people pulling at me every minute, that to assemble the hours of
focussed attention to actually work through a significant amount of
study material, these sorts of immersion courses are beneficial.

Of course, that also assumes that my employer is willing to pay for it,
which they are. If I had to pay, then the economics would be in favor
of cracking a book and taking the fully DIY approach--which is basically
how I've learned nearly everything I know about electronics to date.

Of course, these sorts of courses require a lot of DIY follow-through to
drive things home.

In this case, since I have quite a bit of increasingly complicated
(though still fairly simple by the standards of most experts) FPGA
development to do over the next few years, there will be ample
opportunity to exercise what I have learned.

I think the point is, that there are a lot of practices that aren't
obviated by simply reading a Verilog textbook. Even some of the "learn
by example" books have some shoddy practices.
Click to expand...
Why Verilog? If you have a background in programming you might find
VHDL easier to work with.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
Nico Coesel wrote:
"Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net> wrote:

Hi:

While I'm very able to learn on my own, I feel that at my age and with
so many people pulling at me every minute, that to assemble the hours of
focussed attention to actually work through a significant amount of
study material, these sorts of immersion courses are beneficial.

Of course, that also assumes that my employer is willing to pay for it,
which they are. If I had to pay, then the economics would be in favor
of cracking a book and taking the fully DIY approach--which is basically
how I've learned nearly everything I know about electronics to date.

Of course, these sorts of courses require a lot of DIY follow-through to
drive things home.

In this case, since I have quite a bit of increasingly complicated
(though still fairly simple by the standards of most experts) FPGA
development to do over the next few years, there will be ample
opportunity to exercise what I have learned.

I think the point is, that there are a lot of practices that aren't
obviated by simply reading a Verilog textbook. Even some of the "learn
by example" books have some shoddy practices.

Why Verilog? If you have a background in programming you might find
VHDL easier to work with.
Click to expand...

I thought very carefully about the decision to use Verilog years ago.
My background is electronics, with a bunch of programming, mostly
low-level to go along with it.

But I have to do many things, and sometimes I will do a burst of
logic/embedded work, then go align lasers for 6 months. What I come
back to needs to be as simple as possible.

Verilog is less verbose than VHDL. I consider VHDL to be the Java of
HDLs. I don't need that. So far I have been happy with working with
Verilog. It's fairly easy to understand. I'd just like an immersion
type of experience right now to cover in a few short days all the
details that I need to learn about, even if I don't necessarily commit
them to memory in that short time, or fully get all their implications.

Likewise with the toolset.

Thanks for the comment.

--
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17
 
Mr.CRC <crobcBOGUS@removethissbcglobal.net> wrote:

(snip)

I thought very carefully about the decision to use Verilog years ago.
My background is electronics, with a bunch of programming, mostly
low-level to go along with it.

But I have to do many things, and sometimes I will do a burst of
logic/embedded work, then go align lasers for 6 months. What I come
back to needs to be as simple as possible.

Verilog is less verbose than VHDL. I consider VHDL to be the Java of
HDLs. I don't need that.
Click to expand...
I have worked with Java, and it isn't that wordy. Some have
compared VHDL to ADA, though I haven't worked with ADA enough
to know. I can usually read VHDL enough to figure out what it
does, but won't claim to be able to write it.

Some years ago, I was told that VHDL was more common for FPGA
designs, and verilog for ASIC designs, but I believe even that
isn't true by now.

So far I have been happy with working with Verilog. It's fairly
easy to understand. I'd just like an immersion type of experience
right now to cover in a few short days all the details that I need
to learn about, even if I don't necessarily commit them to memory
in that short time, or fully get all their implications.
Click to expand...
-- glen
 
"Some have compared VHDL to ADA, though I haven't worked with ADA enough t
know."

Both were developed at the behest of the USA DoD, and a cursory examinatio
of example code from each will draw you to the inevitable conclusion tha
VHDL's syntax was derived from that of Ada's. Which should not be
surprise...

Note: 'Ada' is not an acronym, but 'VHDL' is.


---------------------------------------
Posted through http://www.FPGARelated.com
 
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

Mr.CRC <crobcBOGUS@removethissbcglobal.net> wrote:

(snip)

I thought very carefully about the decision to use Verilog years ago.
My background is electronics, with a bunch of programming, mostly
low-level to go along with it.

But I have to do many things, and sometimes I will do a burst of
logic/embedded work, then go align lasers for 6 months. What I come
back to needs to be as simple as possible.

Verilog is less verbose than VHDL. I consider VHDL to be the Java of
HDLs. I don't need that.

I have worked with Java, and it isn't that wordy. Some have
compared VHDL to ADA, though I haven't worked with ADA enough
to know. I can usually read VHDL enough to figure out what it
does, but won't claim to be able to write it.

Some years ago, I was told that VHDL was more common for FPGA
designs, and verilog for ASIC designs, but I believe even that
isn't true by now.
Click to expand...
It depends on personal preference I guess. To me Verilog looks like a
lot of gibberish so I use VHDL. What I also like about VHDL is its
power. VHDL may be more verbose but once you treat it as a programming
language a simple function can reduce the number of typing required
considerably.

A nice example is a priority encoder. If you search with Google for an
example you'll see 9 out of 10 people write an equation for each
output. Only one writes a function consisting of 3 lines which has the
additional advantage of being generic.

And don't get me started on designs which can be adjusted by means of
few simple parameters...

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
Nico Coesel <nico@puntnl.niks> wrote:

(snip, someone wrote)
Verilog is less verbose than VHDL. I consider VHDL to be
the Java of HDLs. I don't need that.

I have worked with Java, and it isn't that wordy. Some have
compared VHDL to ADA, though I haven't worked with ADA enough
to know. I can usually read VHDL enough to figure out what it
does, but won't claim to be able to write it.
Click to expand...
(snip)
It depends on personal preference I guess. To me Verilog looks like a
lot of gibberish so I use VHDL. What I also like about VHDL is its
power. VHDL may be more verbose but once you treat it as a programming
language a simple function can reduce the number of typing required
considerably.
Click to expand...
I mostly write structural verilog, with continuous assignment
and module references. Behavioral (always blocks) mostly for
registers and state machines.

A nice example is a priority encoder. If you search with Google for an
example you'll see 9 out of 10 people write an equation for each
output. Only one writes a function consisting of 3 lines which has the
additional advantage of being generic.
Click to expand...
You mean for each input? It seems, good or bad, that most
synthesis tools do pretty well with the verbose form, though.

Last time I wrote one, for 40 inputs, I did it nested, first
writing the eight input encoder, then five of those, and the
logic to put the result together. I believe it was pipelined,
with a register between the two.

And don't get me started on designs which can be adjusted by means of
few simple parameters...
Click to expand...
-- glen
 
Anyway, I am considering to take the "Comprehensive Verilog" and
"Essentials and Design for Performance" classes by Doulos at Xilinx in Dec.
Just wondering if people think these are worthwhile?
Click to expand...
I started my FPGA development with a comprehensive VHDL course when working
at Nortel 15 years ago!

I think the Doulos courses are considered well structured. I found the tutor to be
good at explaning concepts and he knew his stuff enough to answer any of
our questions at the time.

If your employer's paying for it it's a no-brainer.


On language choice I'm a 99% VHDL user but I believe there are a few
verilog constructs that can bite you if you don't remember what you're
doing. If you're dipping in and out of FPGA development with long breaks
between it might be better to concentrate on VHDL which forces you to
do it right?

As others have said a few macros will cut the amount of typing down
drastically.


Nial.
 
Nial Stewart wrote:
Anyway, I am considering to take the "Comprehensive Verilog" and
"Essentials and Design for Performance" classes by Doulos at Xilinx in Dec.
Just wondering if people think these are worthwhile?

I started my FPGA development with a comprehensive VHDL course when working
at Nortel 15 years ago!

I think the Doulos courses are considered well structured. I found the tutor to be
good at explaning concepts and he knew his stuff enough to answer any of
our questions at the time.

If your employer's paying for it it's a no-brainer.
Click to expand...
Yes it is! The kind of no-brainer I like.

On language choice I'm a 99% VHDL user but I believe there are a few
verilog constructs that can bite you if you don't remember what you're
doing. If you're dipping in and out of FPGA development with long breaks
between it might be better to concentrate on VHDL which forces you to
do it right?
Click to expand...
Well perhaps what I'll do is have my employer pay for "Comprehensive
VHDL" at a later time.

It does look like I'll be doing quite a bit of Verilog for a while, and
some of the most biting concepts have already begun to reach
unforgettable status.

As others have said a few macros will cut the amount of typing down
drastically.


Nial.
Click to expand...

Thanks for the input.


--
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17
 
On Sat, 22 Oct 2011 08:29:15 -0700, "Mr.CRC" wrote:

Nial Stewart wrote:
Anyway, I am considering to take the "Comprehensive Verilog" and
"Essentials and Design for Performance" classes by Doulos at Xilinx in Dec.
Just wondering if people think these are worthwhile?
[...]
It does look like I'll be doing quite a bit of Verilog for a while, and
some of the most biting concepts have already begun to reach
unforgettable status.
Click to expand...
So let's get the disclosure out of the way: I worked for
Doulos until a couple of years ago, parted in a friendly
way, and still have occasional contact with them (but no
financial links at all).

I'd absolutely echo all Nial said. Certainly Doulos (in
common with other reputable training providers) take real
care to provide a good experience for delegates, and offer
good after-course support too. Their Verilog course is
mature, stable and well-maintained, and they don't employ
script-reading droids to do the presentation - you'll get
someone who really knows their stuff and will be happy to
answer your specific questions. The improvement in your
own productivity that a good class can provide will far,
far outweigh the cost of the class and of your lost time
in attending it.

HOWEVER... I would also mention that, as a professional
with a real job to do, you should take a class like that
only if you will have the chance to use its content
immediately when you have completed the class. Even
two weeks' interval between learning and using your new
knowledge will really degrade the effectiveness of any
class, no matter how good. But if you can start to use
the class content immediately, then the excellent course
notes and examples will be a good second-best to having
a tutor/mentor sat next to you while you work.
--
Jonathan Bromley
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top