Doubts on synthesis tool

[rsk]

Hi friends,
These are the doubts iam having with this Leonardo spectrum
synthesis tool.

1)If my design has to work under aparticular fpga technology like
ALTERA,QUICKLOGIC,XILINX for a given "clock" frequency,in such a case
what should i do if i get a negative slack?


2)what is the synthesis flow like pre-optimization next----
to giving netlist ?what are all the steps we do in between?


3)Why the design database is saved to XDB?


4)whats this EDF and XNF?what does they mean?


5)What is the difference between standard optimisation and quick
optimisation and extended optimization? which one is better to
use?



I will be waiting for ur answers .

Thanks to one and all who has sent me the answers to my
queries ..Thanks alot

bye friends

ravi...