S
Sink0
Guest
I am trying to make use of OC PCI Bridge, and it is working fine on
the PCI Target side. But when i am trying to master the bus using my
wishbone slave i was having a wrong behavior from the Wb slave of the
bridge. When i try to read from the PC, the bridge should send a RTY
until the data is ready.... but when i request the first time.. the
slave assert the retry but never disassert, even after i disassert STB
and CYC... i was looking at the verilog code at the pci_wb_slave.v but
i cant find the reason for this behavior.... Any one ever had this
problem? Any one have the contact with Miha Dolenc? I tryed sending an
email to opencores email but i think it does not exist anymore..
Thank you!
the PCI Target side. But when i am trying to master the bus using my
wishbone slave i was having a wrong behavior from the Wb slave of the
bridge. When i try to read from the PC, the bridge should send a RTY
until the data is ready.... but when i request the first time.. the
slave assert the retry but never disassert, even after i disassert STB
and CYC... i was looking at the verilog code at the pci_wb_slave.v but
i cant find the reason for this behavior.... Any one ever had this
problem? Any one have the contact with Miha Dolenc? I tryed sending an
email to opencores email but i think it does not exist anymore..
Thank you!