Doubt in using Verilog vpi function

[priya]

Hi All,

I am working in verilog vpi function.I have doubt in following 32
bit register verilog code.here I gave input to the verilog through
verilog vpi function.



reg32bit verilog code

module Reg32(Q, D, clk, reset);
output [31:0] Q;
input [31:0] D;
input clk, reset;
reg [31:0] Q;

always @(posedge clk or negedge reset)
if (!reset)
Q <= 32'b1;
else
begin
Q <=D;
end
endmodule

module top;
reg [0:31]D;
reg clk,reset;
wire[0:31] Q;
Reg32 r1(Q, D, clk, reset);
initial
begin
$Getinputs_verilog_fromVerilogVpi(top);
end
endmodule





In this code i am getting the D,clk,reset value from the verilog vpi
function.
Q <=D;
In this line i am using non-blocking assign statement to assign D value
to Q value.

if i give D value is 11110000111100001111000011110000 through verilog
vpi function..I didnt get q value correctly.


if i use blocking statement ,i got the correct output.
can we non blocking assign statement in verilog while giving input
thrugh verilog vpi function.



regards,
priya