Doubt in Parallel to serial converter

Hello Folks,

I have below mentiond code which is used to convert a 16bit vector to
serial data at each rising edge. I am not getting the expected output
at signal D_out,can somebody tel me where is the mistake?

Regards,
ALI

-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------
ENTITY PTOS IS
PORT
(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
D_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
D_OUT : OUT STD_LOGIC
);
END PTOS;
-----------------------------------------------------------------
ARCHITECTURE ARCH_PTOS OF PTOS IS
-----------------------------------------------------------------
SIGNAL INT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
-----------------------------------------------------------------
BEGIN

PROC_INP : PROCESS (CLK,LOAD,D_IN)

BEGIN
IF RST = '0' THEN
INT_DATA <= (OTHERS => '0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (LOAD = '1') THEN
INT_DATA <= D_IN;
ELSE
INT_DATA <= (OTHERS =>'0');
END IF;
D_OUT <= INT_DATA(15);
INT_DATA(15 DOWNTO 1) <= INT_DATA(14 DOWNTO 0);
END IF;
END PROCESS PROCESS_INP;
-----------------------------------------------------------------
END ARCH_PTOS;
-----------------------------------------------------------------

 

PROC_INP : PROCESS (CLK,RST) -- CLK and RST in sensitivity list
BEGIN
IF RST = '0' THEN
INT_DATA <= (OTHERS => '0');
D_OUT <= (OTHERS => '0');

ELSIF rising_edge(CLK) THEN
INT_DATA(15 DOWNTO 1) <= INT_DATA(14 DOWNTO 0);

IF (LOAD = '1') THEN
INT_DATA <= D_IN;
END IF;

D_OUT <= INT_DATA(15);
END IF;
END PROCESS PROCESS_INP;

Activate LOAD once every 16 clock cycles.

Try to perform a functional simulation with Modelsim.

Rgds
André

 

[Nicolas Matringe]

Andy Peters a écrit:

I imagine that your output signal D_OUT is always 0, right?

Right but not for the reason you described )

And this assignment is essentially ignored:
INT_DATA(15 DOWNTO 1) <= INT_DATA(14 DOWNTO 0);

Exactly not, it's the only one that is NOT ignored.
int_data is cleared on reset and then never loaded because of this last
statement.

Nicolas

 

[Andy Peters]

Nicolas Matringe wrote:

Andy Peters a écrit:

I imagine that your output signal D_OUT is always 0, right?

Right but not for the reason you described )


And this assignment is essentially ignored:
INT_DATA(15 DOWNTO 1) <= INT_DATA(14 DOWNTO 0);

Exactly not, it's the only one that is NOT ignored.
int_data is cleared on reset and then never loaded because of this last
statement.

OK, you're right -- I was mixing Verilog and VHDL again.

-a