Doubt about decoupling capacitors in high-freq PCBs

[Mayank Kaushik]

Hi,

Im a total newbie to PCB design, i have to build a high-speed PCB for a
board containing an Atmel At91 microcontroller operating at 200MHz,
with RAM, Flash, etc, so im trying to collect info on PCB design.

The question may be a bit misleading, heres the actual dope:
Ive seen high-speed PCBs where not all of the decoupling capacitors are
included on the final board, even though the schematic may mention all
of them.How does one decide which decoupling caps can be safely omitted
in the final design?

Also, in an earlier design using the same controller as above, we had
the RAM and the controller on seperate boards, connedted with a 20cm
long ribbon cable. But the RAM wasnt functioning correctly, we were
getting garbled data when we tried to store stuff on the RAM..could it
be due to the fact that the RAM and the uC were on seperate boards??


Thanks in anticipation,
Mayank

 

[Rick]

If you do a multilayer board with a thin dielectric between the ground
plane and power planes (or even power islands) it doesn't matter much
where you put the caps; the planes themselves are a superb capacitor.
I sometimes add a few SMA connector footprints to a board layout so I
can TDR the planes. As near as my Tek 20 GHz TDR can tell, a typical
power/ground plane pair looks like an ideal capacitor, and adding
bypasses anywhere just makes it look like a bigger ideal capacitor.

But isn't the point of decoupling CAPs twofold - to stabilize the energy
source and to shunt higher frequency signals to ground ? Wouldn't having
only a large capacitance value from the physically large power and ground
planes be counter productive to that ?

 

[Mayank Kaushik]

Hi guys..

One more thing..In such a design, is it absolutely necessary to use
surface mounted caps? Whats the advantage these surface mounted caps
have over normal ones? We have used only normal ceramics and
electrolytic caps till now (both on the main board and the RAM board).
They seemed to work fine on the board, though i cant say anything abt
the RAM

Regards

Mayank

 

In general, how was it determine where the cap's needed to be placed?
What value cap's were choosen?

I was told to seperate the analog and digital ground. Then tie them
together
at the input pins where Vcc entered the board.

If I tried what you mention it would not work!!!!

boats_ranger

 

I was told to seperate the analog and digital ground. Then tie them
together at the input pins where Vcc entered the board.

Good luck. You'll need it with advice like that.

You have my respect!!!

I limit the distance that the bypassed current has to flow
based on its highest significant frequency content and
the magnitude of the disturbance I am willing to allow.

Does this imply placing the cap across the shortest distance from it's
vcc and ground?

thank's boats_ranger

 

[Larry Brasfield]

<boats_ranger@yahoo.com> wrote in message
news:1109056580.344795.96210@z14g2000cwz.googlegroups.com...
....

I limit the distance that the bypassed current has to flow
based on its highest significant frequency content and
the magnitude of the disturbance I am willing to allow.

Does this imply placing the cap across the shortest distance from it's
vcc and ground?

Yes, provided the referent of your "it" is any one of the
set of devices generating the currents being bypassed.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Larry Brasfield]

"Mayank Kaushik" <prehistorictoad2k@yahoo.com> wrote in message
news:1109051497.851221.123270@o13g2000cwo.googlegroups.com...

Hi guys..
Hi.

One more thing..In such a design, is it absolutely necessary to use
surface mounted caps?

That would depend upon what the caps are called upon to do.

Whats the advantage these surface mounted caps
have over normal ones?

With careful placement of the vias that connect a SMD cap to
the planes, the inductance can be kept lower than is possible
when wire leads are attached to a ceramic cap chip. This gets
the resonant frequency up and the minimum impedance down.

We have used only normal ceramics and
electrolytic caps till now (both on the main board and the RAM board).
They seemed to work fine on the board, though i cant say anything abt
the RAM

Of course thru-hole circuits worked for a long time. But the
advantages of surface mount become ever more important
as operating frequency and edge speeds go up.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Bob]

Mayank,

Determining if you've omitted too many capacitors is a difficult question.
The easiest way to tell is to hook up a high-speed scope (with a
differential probe) to the power supply (right at the chip pins or balls).
Then, see if the supply ever dips below its rated limits.

As far as the faulty RAM (with the longer cable), there are (at least) two
possibilities:

1) The setup time required by the RAM or its controller has been violated
due to the longer transit time.
2) The clock line, to the RAM, has not been terminated properly. So, the
clock edges (at the RAM) may not be monotonic.
3) There may be crosstalk, in the cable, causing the clock edges (at the
RAM) to be non-monotonic.

#2 or #3 are the more likely candidates, but it's hard to tell without
taking measurements on your setup.

Bob



"Mayank Kaushik" <prehistorictoad2k@yahoo.com> wrote in message
news:1108969329.410436.60430@l41g2000cwc.googlegroups.com...

Hi,

Im a total newbie to PCB design, i have to build a high-speed PCB for a
board containing an Atmel At91 microcontroller operating at 200MHz,
with RAM, Flash, etc, so im trying to collect info on PCB design.

The question may be a bit misleading, heres the actual dope:
Ive seen high-speed PCBs where not all of the decoupling capacitors are
included on the final board, even though the schematic may mention all
of them.How does one decide which decoupling caps can be safely omitted
in the final design?

Also, in an earlier design using the same controller as above, we had
the RAM and the controller on seperate boards, connedted with a 20cm
long ribbon cable. But the RAM wasnt functioning correctly, we were
getting garbled data when we tried to store stuff on the RAM..could it
be due to the fact that the RAM and the uC were on seperate boards??


Thanks in anticipation,
Mayank

 

[John Larkin]

On 20 Feb 2005 23:02:09 -0800, "Mayank Kaushik"
<prehistorictoad2k@yahoo.com> wrote:

Hi,

Im a total newbie to PCB design, i have to build a high-speed PCB for a
board containing an Atmel At91 microcontroller operating at 200MHz,
with RAM, Flash, etc, so im trying to collect info on PCB design.

The question may be a bit misleading, heres the actual dope:
Ive seen high-speed PCBs where not all of the decoupling capacitors are
included on the final board, even though the schematic may mention all
of them.How does one decide which decoupling caps can be safely omitted
in the final design?

It's common, nearly universal, to design in too many bypass caps; I've
seen boards with hundreds and heard of boards with thousands. Most
people just leave them in, but one can measure rail noise and remove
caps to cut cost.

I know a guy who does dense digital boards and doesn't use bypass caps
at all. Personally, I've never done a board that had too few, so he
may be right.

Also, in an earlier design using the same controller as above, we had
the RAM and the controller on seperate boards, connedted with a 20cm
long ribbon cable. But the RAM wasnt functioning correctly, we were
getting garbled data when we tried to store stuff on the RAM..could it
be due to the fact that the RAM and the uC were on seperate boards??

Unless everything was properly terminated, and the critical sigs were
straddled by grounds in the cable, and the prop delays were
calculated, and there are no ground loops, this can be very bad news.

John

 

[Larry Brasfield]

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX>
wrote in message news:upok11tbomnomgsj0uiuln53pqr9tf7272@4ax.com...
....

It's common, nearly universal, to design in too many bypass caps; I've
seen boards with hundreds and heard of boards with thousands. Most
people just leave them in, but one can measure rail noise and remove
caps to cut cost.

I know a guy who does dense digital boards and doesn't use bypass caps
at all. Personally, I've never done a board that had too few, so he
may be right.

I once designed a MultiBus card with its area divided into
about 1/3 ECL, 1/2 74Fxx TTL, and some analog stuff.
The logic was running near the upper edge of its frequency
range, (some of the time). Much of the logic was stateful
and several different clocks traveled across the board.

According to my calculations, the digital sections needed
a total of about 11 bypass capacitors if well placed. The
board was layed out to meet my placement criteria. While
verifying prototypes, I performed the procedure you just
mentioned. What surprised me was that not only could I
remove all the bypasses, but I could not observe any real
increase in the rail noise after doing so.

Since then, I have been a great fan of adjacent power and
ground planes for digital circuits. Most logic (excepting
ECL) is equally hard on both rails.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[John Larkin]

On Mon, 21 Feb 2005 15:00:48 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

"John Larkin" <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX
wrote in message news:upok11tbomnomgsj0uiuln53pqr9tf7272@4ax.com...
...
It's common, nearly universal, to design in too many bypass caps; I've
seen boards with hundreds and heard of boards with thousands. Most
people just leave them in, but one can measure rail noise and remove
caps to cut cost.

I know a guy who does dense digital boards and doesn't use bypass caps
at all. Personally, I've never done a board that had too few, so he
may be right.


I once designed a MultiBus card with its area divided into
about 1/3 ECL, 1/2 74Fxx TTL, and some analog stuff.
The logic was running near the upper edge of its frequency
range, (some of the time). Much of the logic was stateful
and several different clocks traveled across the board.

According to my calculations, the digital sections needed
a total of about 11 bypass capacitors if well placed. The
board was layed out to meet my placement criteria. While
verifying prototypes, I performed the procedure you just
mentioned. What surprised me was that not only could I
remove all the bypasses, but I could not observe any real
increase in the rail noise after doing so.

Since then, I have been a great fan of adjacent power and
ground planes for digital circuits. Most logic (excepting
ECL) is equally hard on both rails.

If you do a multilayer board with a thin dielectric between the ground
plane and power planes (or even power islands) it doesn't matter much
where you put the caps; the planes themselves are a superb capacitor.
I sometimes add a few SMA connector footprints to a board layout so I
can TDR the planes. As near as my Tek 20 GHz TDR can tell, a typical
power/ground plane pair looks like an ideal capacitor, and adding
bypasses anywhere just makes it look like a bigger ideal capacitor.

And this stuff about microstrip return current getting confused when
"the reference plane changes" is 99.44% nonsense. Some people are
obscessed with this silly return current idea.

If chips can change Icc grossly, like a CPU sleeping and getting an
interrupt or something, you do need something to supply the gross
energy without drooping too much.

John

 

[Larry Brasfield]

"Rick" <rick@nospam.com> wrote in message
news:vozSd.29895$911.1218@fe2.texas.rr.com...
[Apparently quoting John Larkin]

If you do a multilayer board with a thin dielectric between the ground
plane and power planes (or even power islands) it doesn't matter much
where you put the caps; the planes themselves are a superb capacitor.
I sometimes add a few SMA connector footprints to a board layout so I
can TDR the planes. As near as my Tek 20 GHz TDR can tell, a typical
power/ground plane pair looks like an ideal capacitor, and adding
bypasses anywhere just makes it look like a bigger ideal capacitor.


But isn't the point of decoupling CAPs twofold - to stabilize the energy
source and to shunt higher frequency signals to ground ? Wouldn't having
only a large capacitance value from the physically large power and ground
planes be counter productive to that ?

But the point is, the high frequencies need not reach
the larger discrete capacitances. They are shunted
thru the nearby dielectric between the planes.

The fact that higher frequencies are successfully
shunted can be observed in the low magnitude of
voltage disturbances arising from the impulse-like
load currents that accompany output edges.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Larry Brasfield]

<boats_ranger@yahoo.com> wrote in message
news:1109053665.974756.269470@f14g2000cwb.googlegroups.com...

In general, how was it determine where the cap's needed to be placed?

I limit the distance that the bypassed current has to flow
based on its highest significant frequency content and
the magnitude of the disturbance I am willing to allow.

What value cap's were choosen?

I don't recall. Either 10nF or 100nF.

I was told to seperate the analog and digital ground. Then tie them
together at the input pins where Vcc entered the board.

Good luck. You'll need it with advice like that.

If I tried what you mention it would not work!!!!

It worked for me. In fact, it worked so well that I
could not observe an degradation of rail noise. It
changed a little bit in spectrum, but not magnitude.

boats_ranger
--

--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.