doubling clock rate does what to power consumption?

[Ken]

Hi folks,

Been checking the archives for an answer to this one without much luck...

What does doubling the clock rate of a design on an FPGA do to the power
consumption (in general - I am just looking for a rule of thumb here..)?

If you need some assumptions to answer:

Assume:
critical path is a 25-bit carry chain in an adder.
a highly pipelined design occupying most of the device.

Not sure what else would be useful assumptions-wise - please feel free to
add your own!

Also, if I double my clock rate and reduce my hardware by half due to
sharing hardware over 2 clock cycles, obviously the reduced hardware will
reduce power consumotion and the increased clock will increase power
consumption, question is, which is the overriding factor? (the clock I
guess?).

Again, just looking for a rule of thumb.

Cheers,

Ken

 

[Austin Lesea]

Ken,

Easy, just use the power estimator spreadsheet.

http://www.xilinx.com/ise/power_tools/spreadsheet_pt.htm

Austin

PS: generally speaking, if the dynamic power is dominating, CV^2F=P implies
that the power will double if F is doubled, but there are lots of other
fatcors you need to pay attention to, such as what the IOs are doing (did the
data rate double there as well?), etc.



Ken wrote:

Hi folks,

Been checking the archives for an answer to this one without much luck...

What does doubling the clock rate of a design on an FPGA do to the power
consumption (in general - I am just looking for a rule of thumb here..)?

If you need some assumptions to answer:

Assume:
critical path is a 25-bit carry chain in an adder.
a highly pipelined design occupying most of the device.

Not sure what else would be useful assumptions-wise - please feel free to
add your own!

Also, if I double my clock rate and reduce my hardware by half due to
sharing hardware over 2 clock cycles, obviously the reduced hardware will
reduce power consumotion and the increased clock will increase power
consumption, question is, which is the overriding factor? (the clock I
guess?).

Again, just looking for a rule of thumb.

Cheers,

Ken

 

[Nicholas C. Weaver]

In article <blc9hh$p70$1@dennis.cc.strath.ac.uk>,
Ken <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote:

Hi folks,

Been checking the archives for an answer to this one without much luck...

What does doubling the clock rate of a design on an FPGA do to the power
consumption (in general - I am just looking for a rule of thumb here..)?

Back o the envelope..

Dynamic Power = CV^2F.

Static Power = Constant...

Since you aren't scaling the voltage, if you double the frequency,
what happens to the dynamic power?

And given that the leaking (static) power isn't half- the power
dissipation yet.

Also, if I double my clock rate and reduce my hardware by half due to
sharing hardware over 2 clock cycles, obviously the reduced hardware will
reduce power consumotion and the increased clock will increase power
consumption, question is, which is the overriding factor? (the clock I
guess?).

Static vs Dynamic.

Also, logic which changes burns power, so such interleaving will
probably reduce bit-history effects, upping power.


--
Nicholas C. Weaver nweaver@cs.berkeley.edu