double signal affectation

[titi]

Is this an issue that count be affected with two distinct values in the
same rising_edge?

What does happen in such a case?

Illustration:

Signal count : std_logic_vector (7 downto 0);
p_clocks : process (clock,Reset)
begin
if Reset='1' then
count <= x"77";
elsif rising_edge(clock) then
count <= count - '1';
if count = x"00" then
count <= x"77";
....

 

[Mike Treseler]

titi wrote:

What does happen in such a case?

The best way to find out is to
learn vhdl simulation.

Signal count : std_logic_vector (7 downto 0);
p_clocks : process (clock,Reset)
begin
if Reset='1' then
count <= x"77";
elsif rising_edge(clock) then
count <= count - '1';

That '1' would have to be 1 or x"01"

if count = x"00" then

Note that "count" refers the value from
last time, that is, before the decrement,
so that may not do what you expect.

If you prefer to have values follow the code,
as I do, consider using variables rather than
signals for such computations and comparisons.
Some examples:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler