D
Dan
Guest
I'm working on a sync serial interface between 2 processors using 2 data and
1 clock. I had to replace 1 board because I was sending data while it was
off. By sourcing or sinking one of the IO pins, I fried the board. I'm
trying to think of a good way to avoid this. What I'm thinking of is using a
octal (or quad) latch which buffers the IO and is controlled by the 'master'
processor via the OC or enable pin. As long as the output of the latch is
hi-Z then I shouldn't have a problem. Right?
dansteely2001 at yahoo
1 clock. I had to replace 1 board because I was sending data while it was
off. By sourcing or sinking one of the IO pins, I fried the board. I'm
trying to think of a good way to avoid this. What I'm thinking of is using a
octal (or quad) latch which buffers the IO and is controlled by the 'master'
processor via the OC or enable pin. As long as the output of the latch is
hi-Z then I shouldn't have a problem. Right?
dansteely2001 at yahoo