Done Pin Remains Low after JTAG Configuration of V2Pro

A

Adarsh Kumar Jain

Guest
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
 
If the done lines are wired in parallel then any un-configured device will
drive DONE low. Probably a bit late now but it is always worth putting a
jumper or zero ohm resistor from each of the FPGAs DONE connections so that
you can isolate them individually if you need to.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message
news:c1l0tn$6mi$1@sunnews.cern.ch...
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
Click to expand...
 
Did you set the configuration startup clock to
the JTAG clock (versus the default value, which
is CCLK?)

Eric

Adarsh Kumar Jain wrote:
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
Click to expand...
 
Try using a pullup for HALTNEG and TRSTNEG in xilinx constraints editor tool
Ram

"Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message

news:<c1l0tn$6mi$1@sunnews.cern.ch>...
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
Click to expand...
 
Thanks for your suggestions.
We are able to get something out from the Transceivers.
I was using the JTAGClk and John, as you said, too late.
The board was already designed !
I found another issue with ISE. It was ignoring some of my pin assignments
without giving me any warnings or errors.
Particularly, when i do not instantiate a differential clk buffer for an
incoming differential clk (i was trying to get both the P and N out
directly, just to check), the tool was assigning those pins to some dummy
outputs i have just for simulation and debugging.
And these outputs were basically smashing the incoming clk signal.
Is this an issue with ISE or I was doing sthg fundamentally wrong ?
Thanks
Adarsh

"ram" <ramntn@yahoo.com> wrote in message
news:61c2cc9d.0402261956.7513a7bf@posting.google.com...
Try using a pullup for HALTNEG and TRSTNEG in xilinx constraints editor
tool
Ram

"Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message

news:<c1l0tn$6mi$1@sunnews.cern.ch>...
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs
remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such
a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
Click to expand...
 
Did you try "Enable Internal Done Pipe" in the
startup options? It would seem that otherwise the
device waits for the Done pin to go high.

Another approach I've used with a similar setup
(except V2, not V2pro) is to generate a dummy project
to load into each of the "unused" parts in the chain.
When all parts are loaded, the Done pin should go high.

"Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message

news:<c1l0tn$6mi$1@sunnews.cern.ch>...
Hi,
I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
programming succeeded, the done pin remains low and all the outputs remain
High.
I have 8 V2P7s in parallel and they all the drive the same DONE line.
What happens when we just program one of the 8 devices with JTAG in such a
setup ?
PLEASE HELP !!!
Thanks in advance,
Adarsh
Click to expand...
 
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