Doesn't RC support this statement?

[ppc]

Can anyone confirm this?

*************************************************************************
module test (clk, reset, in, out);

`define kLvEdge negedge
parameter kLv = 1'b0;

input clk, reset, in;
output out;
reg out;

always @(posedge clk or `kLvEdge reset)
begin
if (kLv == reset)
//if (reset == kLv)
//if (reset == 1'b0)
out <= kLv;
else
out <= in;

end
endmodule
*************************************************************************

This the error when running read_hdl

*************************************************************************
rc:/> read_hdl test.v
if (kLv == reset)
|
Error : Expecting a comparison to a signal in the edge event list
[VLOGPT-431] [read_hdl]
: in file test.v at line 12, column 11
endmodule
|
Error : More than one clock has been defined in the always block
[VLOGPT-413] [read_hdl]
: in file test.v at line 20, column 9
Failed on read_hdl test.v
*************************************************************************

The statement "if (reset == kLv)" also not alright. Only "if (reset ==
1'b0)" is okay.

 

[EdA]

This works fine in the GPL version of "cver":

/Ed

 

[ppc]

"EdA" <ed.arthur@gmail.com> wrote in message news:<1113045859.767351.161780@g14g2000cwa.googlegroups.com>...

This works fine in the GPL version of "cver":

/Ed

I believe it is okay with all simulators. But I'm not sure about the
synthesizer tool.

 

[Paul]

ppc wrote:

Can anyone confirm this?


*************************************************************************
module test (clk, reset, in, out);

`define kLvEdge negedge
parameter kLv = 1'b0;

input clk, reset, in;
output out;
reg out;

always @(posedge clk or `kLvEdge reset)
begin
if (kLv == reset)
//if (reset == kLv)
//if (reset == 1'b0)
out <= kLv;
else
out <= in;

end
endmodule

*************************************************************************

This the error when running read_hdl


*************************************************************************
rc:/> read_hdl test.v
if (kLv == reset)
|
Error : Expecting a comparison to a signal in the edge event list
[VLOGPT-431] [read_hdl]
: in file test.v at line 12, column 11
endmodule
|
Error : More than one clock has been defined in the always block
[VLOGPT-413] [read_hdl]
: in file test.v at line 20, column 9
Failed on read_hdl test.v

*************************************************************************

The statement "if (reset == kLv)" also not alright. Only "if (reset
==
1'b0)" is okay.

The check (reset == 1'b0) is kind of redundant since it is implied by
the negedge edge specifier. So it doesn't make sense to allow the
reset test value to be parameterizable. Do other synthesis tools
support this?

Paul Graham