Doesn't RC support this statement?

[ppc]

Can anyone confirm this?

*************************************************************************
module test (clk, reset, in, out);

`define kLvEdge negedge
parameter kLv = 1'b0;

input clk, reset, in;
output out;
reg out;

always @(posedge clk or `kLvEdge reset)
begin
if (kLv == reset)
//if (reset == kLv)
//if (reset == 1'b0)
out <= kLv;
else
out <= in;

end
endmodule
*************************************************************************

This the error when running read_hdl

*************************************************************************
rc:/> read_hdl test.v
if (kLv == reset)
|
Error : Expecting a comparison to a signal in the edge event list
[VLOGPT-431] [read_hdl]
: in file test.v at line 12, column 11
endmodule
|
Error : More than one clock has been defined in the always block
[VLOGPT-413] [read_hdl]
: in file test.v at line 20, column 9
Failed on read_hdl test.v
*************************************************************************

The statement "if (reset == kLv)" also not alright. Only "if (reset ==
1'b0)" is okay.