Doese CoreGen RAM can be simulated in ModelSim?

Z

Zhi

Guest
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
 
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
Click to expand...
Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu
 
On 5ÔÂ2ČŐ, ĎÂÎç1Ęą16ˇÖ, Magne <magnem...@yahoo.no> wrote:
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks

Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu
Click to expand...
Yes, I did compile the libraries first. The error happened on the
process of step simulation.
 
Zhi wrote:
On 5ÔÂ2ČŐ, ĎÂÎç1Ęą16ˇÖ, Magne <magnem...@yahoo.no> wrote:
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu

Yes, I did compile the libraries first. The error happened on the
process of step simulation.

Is there a error message?
Click to expand...
 
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6
# while executing
# "error $winName"
# (procedure "view" line 82)
# invoked from within
# "view source"
# (procedure "vsimcmd::viewProcessSource" line 2)
# invoked from within
# "vsimcmd::viewProcessSource /testbench/uut/u0/u0/line__93705"
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
# 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
By the way, I also downloaded the Dual Port Block RAM v6.1 from
http://www.xilinx.com/support/software/coregen/71i_coregen_examples.htm
When I run the tb in ModelSim, I got the same error information.
Anybody can try once the example? Maybe I get mistakes on other
places. Thank you.
Magne wrote:
Zhi wrote:
On 5ÔÂ2ČŐ, ĎÂÎç1Ęą16ˇÖ, Magne <magnem...@yahoo.no> wrote:
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu

Yes, I did compile the libraries first. The error happened on the
process of step simulation.

Is there a error message?
Click to expand...
 
On May 2, 12:09 pm, Zhi <threeinchn...@gmail.com> wrote:
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6
#     while executing
# "error $winName"
#     (procedure "view" line 82)
#     invoked from within
# "view source"
#     (procedure "vsimcmd::viewProcessSource" line 2)
#     invoked from within
# "vsimcmd::viewProcessSource /testbench/uut/u0/u0/line__93705"
#     ("after" script)
#    2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
#    1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
By the way, I also downloaded the Dual Port Block RAM v6.1 fromhttp://www..xilinx.com/support/software/coregen/71i_coregen_examples.htm
When I run the tb in ModelSim, I got the same error information.
Anybody can try once the example? Maybe I get mistakes on other
places. Thank you.



Magne wrote:
Zhi wrote:
On 5月2日, 下午1时16分, Magne <magnem...@yahoo.no> wrote:
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu

Yes, I did compile the libraries first. The error happened on the
process of step simulation.

Is there a error message?- Hide quoted text -

- Show quoted text -

By the way, I also downloaded the Dual Port Block RAM v6.1 from
http://www.xilinx.com/support/software/coregen/71i_coregen_examples.htm
When I run the tb in ModelSim, I got the same error information.
Anybody can try once the example? Maybe I get mistakes on other
places. Thank you.
Click to expand...

I compiled the Dual Port Block RAM v6.1 testbench suite. I got a
compile error in my_dp_bram.vhd. Xilinx Answer Record # 24819 fixed
this problem. From there I ran the simulation and it said it
completed successfully. Did you get any compile errors?

Good luck.

-Newman
 
Thanks Newman. I don't have compile error. I use ModelSim SE plus
6.1d. I guess the problem you mentioned has solved in this edition. I
have tried again and just push the Run button. Sounds everything is
ok.

I am used to debug the program by 'Step'. It is convenient for me to
watch the change. I don't know if it is a correct way to debug
program. That error only happens on the 'Step' simulation. It got me
mad. Thank you again for your trying the program.
Newman wrote:
On May 2, 12:09 pm, Zhi <threeinchn...@gmail.com> wrote:
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6
#     while executing
# "error $winName"
#     (procedure "view" line 82)
#     invoked from within
# "view source"
#     (procedure "vsimcmd::viewProcessSource" line 2)
#     invoked from within
# "vsimcmd::viewProcessSource /testbench/uut/u0/u0/line__93705"
#     ("after" script)
#    2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
#    1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1400_6}
By the way, I also downloaded the Dual Port Block RAM v6.1 fromhttp://www.xilinx.com/support/software/coregen/71i_coregen_examples.htm
When I run the tb in ModelSim, I got the same error information.
Anybody can try once the example? Maybe I get mistakes on other
places. Thank you.



Magne wrote:
Zhi wrote:
On 5月2日, 下午1时16分, Magne <magnem...@yahoo.no> wrote:
Zhi wrote:
I simulate a program which included a coregen RAM. ModelSim always
gives error information. If I only remove this component, other part
will work correctly. Does anybody has the experience to simulate the
codes including coregen component.
Thanks
Hello Zhi,

you need to compile the simulation libraries from Xilinx ISE:
1. In ISE, select the device in the sources window
2. find the the "Compile HDL Simulation libraries", right click and
select "Properties"
3. Set your preferences in dialog and apply and run the process.
4. Make a library reference to the compiled library from modelsim.

mamu

Yes, I did compile the libraries first. The error happened on the
process of step simulation.

Is there a error message?- Hide quoted text -

- Show quoted text -

By the way, I also downloaded the Dual Port Block RAM v6.1 from
http://www.xilinx.com/support/software/coregen/71i_coregen_examples.htm
When I run the tb in ModelSim, I got the same error information.
Anybody can try once the example? Maybe I get mistakes on other
places. Thank you.


I compiled the Dual Port Block RAM v6.1 testbench suite. I got a
compile error in my_dp_bram.vhd. Xilinx Answer Record # 24819 fixed
this problem. From there I ran the simulation and it said it
completed successfully. Did you get any compile errors?

Good luck.

-Newman
Click to expand...
 
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