Does VHDL have a statement similar to "event" in Verilog?

[news reader]

I use "event" to trigger comparison in Verilog testbenches.
Are there similar statements in VHDL?

Thanks.

 

[Eli Bendersky]

On Jul 1, 11:12 am, "news reader" <newsrea...@google.com> wrote:

I use "event" to trigger comparison in Verilog testbenches.
Are there similar statements in VHDL?

Thanks.

Depends on what you need exactly, but you should probably check out
these attributes:

'event
'stable
'quiet
'transaction
'active

(http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm)
for examples

 

[Evan Lavelle]

On Sun, 1 Jul 2007 17:12:15 +0800, "news reader"
<newsreader@google.com> wrote:

I use "event" to trigger comparison in Verilog testbenches.
Are there similar statements in VHDL?

Do you mean named events (ie. event X/->X/@X?) This is easy - just
make X a signal in a package; any architecture which can see the
package can then drive or respond to the signal (google for 'global
signal' if you haven't used package signals before).

The obvious implementation is to make X a std_logic, manually toggle
it when you want to raise an event, and test for X'event in an if
statement (something like "if X='1' and X'event", like waiting for a
clock edge).

A better solution is to use X'transaction. When you raise the signal,
you now don't need to change its value; X'transaction automatically
toggles for you, even if you always assign the same value to X. You
can use X'transaction directly inside a sensitivity list, so that

always
begin
@hierarchical_path.X
...
end

becomes the (almost) equivalent:

process
begin
...
wait on X'transaction;
end process;

Even better, you can make your global signal a record, and pass useful
information to your receiver process, which is much more klunky in the
Verilog version. To do this, load the required data into a variable of
the record type, and then assign your complete variable to signal X.

Evan