Does using assertions for verification mean contamination of

Hi all,
Is there any way to use assertions in verification without
contaminating the existing design code ? In the sample program which I
had previously posted on this group
(http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/de4cbecb7d39cf6b/67fa44eb8d7e5a91?q=assert_always&rnum=2#67fa44eb8d7e5a91)I
had written the assertions as part of the source file itself.

What can I do to put the assertion in some other file and somehow still
use it by including that file ?

Any answers to this will most certainly be appreciated.

Thanks in advance and best regards,
Amit.