Starting from version 2002.05, HDL Compiler (Presto Verilog) supports
the following Verilog 2001 constructs:
Expanded ANSI C-style port declaration:
---------------------------------------
You can list port types and define parameters in the module statement:
module foo #(parameter WIDTH=4)
( bar [WIDTH-1:0] in, b [WIDTH-1:0] out);
Casting operators:
------------------
Allows sign control; preserves the value of the argument. Casting
operators are $signed(), $unsigned().
Parameter passing by name:
--------------------------
Allows setting parameters on subdesigns by parameter name; it is not
sensitive to number or declaration order of parameters. You need to
specify only the subset of parameters you want to set. For example,
mymod (.my_param1(1000)) my_instance(...);
Implicit event expression list:
-------------------------------
makes always blocks sensitive to any variable read:
(@*)
Signed/unsigned constants, parameters, nets, and registers
----------------------------------------------------------
Example of signed nets:
module adder (input [2:0] a; input [2:0] b; output [3:0] z);
wire signed [2:0] x = a;
wire signed [2:0] y = b;
assign z = x - y; // This will result in a signed adder
endmodule
Multidimensional arrays of variables or nets
--------------------------------------------
Example:
reg [3:0] Z [0:3] [0:7] [0:3];
Variable part select addressing ([+:] and [-:] operators) Variable
part-select allows you to select a fixed-width group of bits from a
vector by using a variable base address.
Power Operator (**)
-------------------
The ** power operator raises the value of its first operand to the
power of the second operand:
module m (a, z);
input [3:0] a;
output [7:0] x, y, z;
assign z = 2 ** a;
assign x = a ** 2;
assign y = b ** c // where b and c are constants
endmodule
Arithmetic shift operators (<<< and >>>
----------------------------------------
These operators allow you to shift an expression to the right or to
left and still maintain the sign of the value.
New compiler directives `ifndef, `elsif, `undef
-----------------------------------------------
Comma-separated sensitivity lists
---------------------------------
Signals in the sensitivity list can be separated with commas.
Arrays of instances
-------------------
This feature enables instantiations of modules that contain a range
specification.
Regards,
Alexander Gnusin
www.TCLforEDA.net
