P
Peng Yu
Guest
Hi,
HDL Complier(Presto Verilog) support ANSI Style Declarations for
parameter. But Behavioral Compiler doesn't. Is that correct?
I tried the following code.
module parameter_test #(parameter WIDTH = 8)(output [WIDTH - 1:0] out,
input [WIDTH - 1:0] a, input[WIDTH - 1:0] b);
assign out = a + b;
endmodule
"analyze -s -f verilog parameter_test.v" produce an error.
"analyze -f verilog parameter_test.v" doesn't produce any errors.
In Chapter 8 of HDL Compiler (Presto Verilog) Reference Manual,
there are the verilog-2001 features that are supported by it. But I
don't find corresponding chapter in Behavioral Compiler Verilog User
and Modeling Guide.
Does somebody know where I can find those information for BC?
Thanks!
Peng
HDL Complier(Presto Verilog) support ANSI Style Declarations for
parameter. But Behavioral Compiler doesn't. Is that correct?
I tried the following code.
module parameter_test #(parameter WIDTH = 8)(output [WIDTH - 1:0] out,
input [WIDTH - 1:0] a, input[WIDTH - 1:0] b);
assign out = a + b;
endmodule
"analyze -s -f verilog parameter_test.v" produce an error.
"analyze -f verilog parameter_test.v" doesn't produce any errors.
In Chapter 8 of HDL Compiler (Presto Verilog) Reference Manual,
there are the verilog-2001 features that are supported by it. But I
don't find corresponding chapter in Behavioral Compiler Verilog User
and Modeling Guide.
Does somebody know where I can find those information for BC?
Thanks!
Peng