Does Modelsim ASE support SystemVerilog?

[Petter Gustad]

Does Modelsim ASE (Altera Starter Edition) support SystemVerilog?

It appears to compile fine. But I get a runtime error (Error loading
design) and I don't know if it's because it's not supported or if I'm
not supplying the right arguments to vsim (previously I've only used
VCS for my SystemVerilog simulations).

//Petter
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..sig removed by request.

 

[Jonathan Bromley]

On Thu, 19 Aug 2010 15:41:59 +0200, Petter Gustad wrote:

Does Modelsim ASE (Altera Starter Edition) support SystemVerilog?

As far as I'm aware, everything except randomization,
coverage and assertions.

It appears to compile fine. But I get a runtime error (Error loading
design) and I don't know if it's because it's not supported or if I'm
not supplying the right arguments to vsim (previously I've only used
VCS for my SystemVerilog simulations).

AFAIK you don't need any special vsim args to support SV.
As long as you've used the -sv switch to vlog, or used
a .sv file extension, you should be OK.

"Error loading design" is about as helpful as
a not very helpful thing, but it's usually caused by
some grotesque parameterization error. Any other
diagnostic?
--
Jonathan Bromley

 

[Petter Gustad]

Jonathan Bromley <spam@oxfordbromley.plus.com> writes:

"Error loading design" is about as helpful as
a not very helpful thing, but it's usually caused by
some grotesque parameterization error. Any other
diagnostic?

Unfortunately not, but it could be because I tried to use a program as
top level. I also tried some code and commands I found on the net,
which I assume have been tested:

http://www.asicguru.com/system-verilog/sv-classes/simple-class/90/

Running the code and set of commands given in the URL above gives
nothing but:

vsim -c test
Reading /opt/altera/10/modelsim_ase/tcl/vsim/pref.tcl

# 6.5e

# vsim -c test
# Error loading design
Error loading design


However, if I use a module as top level wrapped around a program I get
a clue:

# ** Fatal: (vsim-3904) SystemVerilog Program Blocks are not supported in Modelsim PE.

Which sort of answered my question...

That raises another question: Which is the best (in terms of
compatibility and speed) simulator for mixed simulations (SV
testbenches and VHDL designs), Questa or VCS-MX?

Petter

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[Jonathan Bromley]

On Thu, 19 Aug 2010 23:33:59 +0200, Petter Gustad wrote:

it could be because I tried to use a program as
top level.

OK. The reason I never met this was that I just don't
use programs any more - they had their place in earlier
versions of SV, but they're just syntactic noise now.
Turn the program into a module instead.

I also tried some code and commands I found on the net,
which I assume have been tested:
http://www.asicguru.com/system-verilog/sv-classes/simple-class/90/

"Tested" and "works with a later version of SV tools" are not
necessarily the same thing That code is OK; but it
would also be OK under the transformation s/program/module/g
and then you would discover that ModelSim PE will refuse to
do the randomization for you.

Chances are the author was using VCS, which in some earlier
versions would not allow classes outside of a program block.
That restriction was lifted a long time ago, although if you
are using a fairly ancient version of VCS you may still need
the command-line switch "-ntb_opts dtm". I think that option
became irrelevant in one of the 2008 versions, but I'm not sure.

However, if I use a module as top level wrapped around a program I get
a clue:
# ** Fatal: (vsim-3904) SystemVerilog Program Blocks are not supported in Modelsim PE.
Which sort of answered my question...

Yup. Didn't know that. Thanks!

That raises another question: Which is the best (in terms of
compatibility and speed) simulator for mixed simulations (SV
testbenches and VHDL designs), Questa or VCS-MX?

There's no way I can answer that without upsetting lots of
people. Don't forget that Cadence IUS also supports mixed
language, and the folks at Aldec are well on the way to
having that too in their high-ened Riviera simulator -
it may even have full SV support already, I'm not sure.

However, I can say with honesty and confidence that both now
support a very wide range of SV language. Note that the UVM
class library is now fully supported by all three big-name
tools, a key sign of maturity in their SystemVerilog support.

I have never made serious use of VCS-MX in mixed VHDL/SV
designs, but I have no reason to doubt it would work OK.
Of course there are the usual SV/VHDL language collisions
(keywords used as instance names, case sensitivity, ...)
and each vendor has subtly different solutions to those
problems, so it pays to read the docs.

I wouldn't like to comment on the speed issue. Simulation
is never fast enough but in real life I've never had
a real speed problem with any mainstream tools. But then,
I don't do big gate-level simulations. It is definitely
true that there are differences between the tools in
speed of random constraint solving, but it also seems to
be true that you can find examples that bring one tool to
a crawl and work fine on others - and also the other way
around. So even if I were able to say "X is better" from
experience, I would surely not be telling the whole truth.

cheers
--
Jonathan Bromley

 

[Petter Gustad]

Jonathan Bromley <spam@oxfordbromley.plus.com> writes:

Thank you for your extensive reply Jonathan.

There's no way I can answer that without upsetting lots of
people.

Yea, I was fearing that would be the case for most users....

I guess the best thing is to request an eval version and then play
with my code. However, I've been a VCS user since the Chronologic days
and tend to prefer VCS, but I've never used VCS for VHDL.

speed of random constraint solving, but it also seems to
be true that you can find examples that bring one tool to
a crawl and work fine on others - and also the other way

This is a good point that I'll keep in mind.

//Petter

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