Does anyone use Cadence Testbuilder?

[PCBman]

I was wondering if anyone used Cadence's Testbuilder as a higher-level
verification
language... I know it's free, but I did not see many posts in google's
archives, which
leads me to believe (perhaps erroneously) that the practicing industry
didn't adopt it.

What's the most appropriate way to verify (functionally) a 10/100 ethernet
MAC?
I've heard the terms "constrained random testbenches" thrown around quite a
bit,
and the books I've skimmed say this approach is the wave of the future. Or
does someone know of vendors (or open-source) verification-library for a
10/100
core?

 

[Ajeetha (www.noveldv.com)]

Hi,

On Mar 14, 10:55 am, "PCBman" <a...@anon.com> wrote:

I was wondering if anyone used Cadence's Testbuilder as a higher-level
verification
language... I know it's free, but I did not see many posts in google's
archives, which
leads me to believe (perhaps erroneously) that the practicing industry
didn't adopt it.

I agree, the Testbuilder's new avatar is SCV (atleast that's what I
understand). I heard some small startups use it, but not much in news.
More importantly the original creator of it is more onto Specman and
SystemVerilog now. So I would SV is the way to go.

What's the most appropriate way to verify (functionally) a 10/100 ethernet
MAC?
I've heard the terms "constrained random testbenches" thrown around quite a
bit,
and the books I've skimmed say this approach is the wave of the future. Or

Sure SV seems to be best fit going forward.

does someone know of vendors (or open-source) verification-library for a
10/100
core?

Sure there are, see Synopsys DW VIP for instance. If you own DC
license you have it!

Of-course there are several startups in this area of creating SV VIPs.
My company specializes in SystemVerilog based services including VIP
creation.

Good Luck
Ajeetha, CVC
www.noveldv.com