P
phil
Guest
Hello all,
I am currently a PhD student at the University of Wisconsin-Madison.
I am working on research where I'm interfacing CPUs directly with
reconfigurable logic. Part of this work (and part of my thesis) is
going to require me to have area estimates of portions of my interface
system. Having these estimates is useful for two reasons: first, it
allows me to better estimate the overhead (in terms of area) of the
interface I've designed between the reconfigurable fabric and the
cache hierarchy, and second, it will allow me to make better
comparisons between using reconfigurable accelerators as compared to
using other accelerator architectures such as vector processing units
and GPUs.
I would be most interested in Xilinx 65nm Virtex 5 devices (as the
reconfigurable fabric I'm simulating in my research is assumed to be
similar to the Virtex-5, and I use timing and area estimates for my
accelerators using this device), in particular the LX 155 device,
although any of them would likely prove to be useful for at least
coming up with a ballpark estimate. If this isn't available, I'd be
open to other recent devices, as I could likely extrapolate an
approximate area, which would allow me to make better educated guesses
concerning the system.
These numbers would be useful to my work even if I can't publish exact
figures, but only rough estimate comparisons. Any help would be
greatly appreciated though.
thanks,
Phil Garcia
I am currently a PhD student at the University of Wisconsin-Madison.
I am working on research where I'm interfacing CPUs directly with
reconfigurable logic. Part of this work (and part of my thesis) is
going to require me to have area estimates of portions of my interface
system. Having these estimates is useful for two reasons: first, it
allows me to better estimate the overhead (in terms of area) of the
interface I've designed between the reconfigurable fabric and the
cache hierarchy, and second, it will allow me to make better
comparisons between using reconfigurable accelerators as compared to
using other accelerator architectures such as vector processing units
and GPUs.
I would be most interested in Xilinx 65nm Virtex 5 devices (as the
reconfigurable fabric I'm simulating in my research is assumed to be
similar to the Virtex-5, and I use timing and area estimates for my
accelerators using this device), in particular the LX 155 device,
although any of them would likely prove to be useful for at least
coming up with a ballpark estimate. If this isn't available, I'd be
open to other recent devices, as I could likely extrapolate an
approximate area, which would allow me to make better educated guesses
concerning the system.
These numbers would be useful to my work even if I can't publish exact
figures, but only rough estimate comparisons. Any help would be
greatly appreciated though.
thanks,
Phil Garcia