does anybody use systemc in FPGA flow?

[pini_kr]

Hi

I just wanted to know if people use systemc in FPGA flow. systemc can b
used for cycle accurate simulation, where it can replace RTL. In thi
mode test-benches will usually take advantage of c++ and SCV (fo
writing constraints).
For big designs where RTL completion takes a lot of time systemc can b
used for LT or AT simulations ( Loosely Timed, Approximately Timed
TLM).

Pin
--------------------------------------
Posted through http://www.FPGARelated.com

 

[Tim Wescott]

On Sat, 11 Apr 2015 01:16:37 -0500, pini_kr wrote:

Hi

I just wanted to know if people use systemc in FPGA flow. systemc can be
used for cycle accurate simulation, where it can replace RTL. In this
mode test-benches will usually take advantage of c++ and SCV (for
writing constraints).
For big designs where RTL completion takes a lot of time systemc can be
used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM).

Are you asking a question or pushing an advertisement? I doubt there are
many on the group who don't know what SystemC is.

Proper capitalization may help -- "systemc" looks like a misspelling of
"systemic". SystemC looks like -- well, SystemC.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Alan Fitch]

On 12/04/15 07:33, Tim Wescott wrote:

On Sat, 11 Apr 2015 01:16:37 -0500, pini_kr wrote:

Hi

I just wanted to know if people use systemc in FPGA flow. systemc can be
used for cycle accurate simulation, where it can replace RTL. In this
mode test-benches will usually take advantage of c++ and SCV (for
writing constraints).
For big designs where RTL completion takes a lot of time systemc can be
used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM).

Are you asking a question or pushing an advertisement? I doubt there are
many on the group who don't know what SystemC is.

Proper capitalization may help -- "systemc" looks like a misspelling of
"systemic". SystemC looks like -- well, SystemC.

The OP might be interested in this:

http://www.testandverification.com/conferences/verification-futures/2015-europe/speaker-andy-lunness-bluwireless-technology/

It's a verification paper, but the design flow was also in SystemC,

regards
Alan

--
Alan Fitch

 

[Sharad]

On Saturday, April 11, 2015 at 2:16:41 PM UTC+8, pini_kr wrote:

Hi

I just wanted to know if people use systemc in FPGA flow. systemc can be
used for cycle accurate simulation, where it can replace RTL. In this
mode test-benches will usually take advantage of c++ and SCV (for
writing constraints).
For big designs where RTL completion takes a lot of time systemc can be
used for LT or AT simulations ( Loosely Timed, Approximately Timed
TLM).

Pini
---------------------------------------
Posted through http://www.FPGARelated.com

I am wondering what has SystemC got to do with FPGA design flow. If you are asking about support for synthesizable subset of SystemC , Xilinx and Altera do not support it in their FPGA flows (Quartus, ISE and Vivado). But it is supported in Vivado HLS. If you use HLS for FPGA designs, then yes, you can use SystemC directly. Of course, even outside of HLS, one can use SystemC...depends on how many different models of our design we want to make.

 

On Saturday, April 11, 2015 at 9:16:41 AM UTC+3, pini_kr wrote:

Hi

I just wanted to know if people use systemc in FPGA flow. systemc can be
used for cycle accurate simulation, where it can replace RTL. In this
mode test-benches will usually take advantage of c++ and SCV (for
writing constraints).
For big designs where RTL completion takes a lot of time systemc can be
used for LT or AT simulations ( Loosely Timed, Approximately Timed
TLM).

Pini
---------------------------------------
Posted through http://www.FPGARelated.com

I am currently using SystemC to model a memory hierarchy that will later be used on FPGAs. At this point it is a TLM model so it's pretty abstract. Still have not decided if I will try to refine to RTL with SystemC or jump directly to VHDL once the behavior is validated.

However, I am also curious about how often people use it for FPGA design, if it is worth it.

Cheers,