Does anybody know why this would oscillate (LDO)?

[Hammy]

Does anybody know why this would oscillate?

Schematic 5.1V LDO 2Ma - 15Ma

http://i36.tinypic.com/fk78ub.png

According to the bode plot this loop should be stable (85 deg PM, 74
kHz crossover at 20db/decade).

http://i35.tinypic.com/ndwwwk.png

I'm using a 4.7uf ceramic X5R cap (C2) on the output.R11 and C4 place
a zero at 8kHz. I thought it might just be the EA model but I bread
boarded it and yep she's definitely unstable.

Spice transient 2mA to 15mA load step.

http://i37.tinypic.com/2lk2y5x.png

What am I missing?

 

[Hammy]

On Sat, 30 Aug 2008 18:33:48 -0700, "Bob Eld" <nsmontassoc@yahoo.com>
wrote:

This circuit has positive feedback with a time constant and far greater than
unity gain. That's how you make oscillators.

How is U7 connected and why is C4, R11 connect from the output to the
non-inverting input of the op-amp.

If this thing didn't oscillate, there would be something wrong.

I'm following the example here.

Basic P-MOS LDO. Ask The Applications Engineer-37

http://i38.tinypic.com/1o64hz.png

I'm following this Appnote from National for using a ceramic cap. They
have an NPN output driving the pass PNP. Would you recommend this.

http://i35.tinypic.com/4t33uq.png

AN-1482 LDO Regulator Stability Using Ceramic Output Capacitors

http://www.national.com/an/AN/AN-1482.pdf

The regulator is stable with 20mV ripple when I use two 2.2uf Tant
caps with 1.75 ohms esr. And a small integrator cap from the positive
terminal to output and a small cap across the top of the divider.

I thought I would try to use one 805 ceramic mainly for it's small
size.

The P-mosfet (U7) is connected source to input drain to output gate to
MCP6002 output through a 10 ohm R.It is on a breadboard with some long
leads.

Could you reccomend any other application notes or material that goes
in more detail on stabilizing LDO's with ceramic output caps.

Thanks

 

[Hammy]

On Sun, 31 Aug 2008 12:48:47 +0100, "Andrew Holme" <ah@nospam.co.uk>
wrote:

The Rcomp and Ccomp feedback needs to be negative i.e. it needs to go to the
inverting input. This means you need a resistor in series with the Vref, or
you add an NPN output transistor with suitable collector resistor to
discharge the PMOS gate.



Yes thank you I think that does it

I'm not sure I'm calculating the gain required for a desired crossover
frequency correctly. For example this is the open loop Bode plot of
the regulator (uncompensated).

http://i35.tinypic.com/4g2qkg.png

From this I read a crossover Frequency of 20 kHz and a PM of 14.267.
if I wanted a crossover at say 100kHz the bode plot says I need to
provide 26dB (19.953) of gain.

New schematic with compensation components.

http://i36.tinypic.com/1qk8sx.png

R3= 1k

So for a gain of 19.953

R4= R3 x 19.953
=19.953k ohms

To place a zero Fz at say 6kHz.

C4= 1/R4xFz
= 1/R4x 6Khz
=8.353nf

According to this bode plot:

http://i35.tinypic.com/2my6tms.png

The calculated components give a crossover frequency at 6.5341kHz,PM
of 79.619.What am I doing wrong?

Thanks for your help.

 

[Hammy]

On Sun, 31 Aug 2008 07:55:21 -0700, "Bob Eld" <nsmontassoc@yahoo.com>
wrote:

Note that in the above circuits that the overall feedback is negative and
that the compensation is also negative feedback around the internal op-amp
to the inverting input.

I think that is right, it looks like U7 is connected source to the positive
voltage source and the drain to the output. That makes sense from a voltage
drop point of view but it does add an inversion in the signal path.

That additional inversion causes confusion about which input is inverting
and which is noninverting on the op-amp. Overall, the + and - switch but
locally around the amp, they don't. In other words, the compensation is
simply to the wrong input pin on the amp.

In general circuits with emitter or source follower outputs perform better
than collector or drain outputs because the output impedance is lower even
without feedback and no additional voltage gain is added to an already very
high gain op-amp circuit.

All gain stages add an additional pole to the frequency response. Op-amps
normally have two internal gain stages giving a two pole response with a
maximum phase shift of 180 deg. When you add a third gain stage, you
automatically add an addional phase shift ultimately to 270 degrees at the
highest frequencies. You also give more total gain to deal with.

This makes compensation more difficult and adds concerns with overshoot,
undershoot, rise time, and poor damping. I suspect that even if you get the
circuit to work ok in the steady state, that it will have poor transient
response and be unable to quickly and accurately respond to changes line and
load conditions.


Well after a bit of experimentation this gives me 32kHz BW,PM of 50.

http://i33.tinypic.com/2afegbb.png

Simulated transient response. This is the worst case load for it 38kHz
10% duty. 2mA to 15mA load step.

http://i34.tinypic.com/2u9mqkl.png

This is the actual measured ripple with worst case load.I'm pretty
sure that those narrow spikes are inductive from all the long leads on
my breadboard.

http://i38.tinypic.com/2zjhny0.jpg

At least I have something to work with I can play with it some more
once I do a layout. CH2 BLUE is the output ripple 20mV division. CH1
is the gate pulses to a FET for a pulsed load.

Thanks for your help everyone any further advice is welcome

 

[Hammy]

On Sun, 31 Aug 2008 13:58:06 -0700, "Bob Eld" <nsmontassoc@yahoo.com>
wrote:

The "ripple" pic, http://i34.tinypic.com/2u9mqkl.png doesn't look right to
me. If I read the time axis right (big if) it looks like it is oscillating
at about 30kHz. I doubt that has anything to do with lead inductance. If
true, I suspect amplifier stability is questionable for the reasons I
mentioned above. It is ALWAYS troublesome to add another gain stage to an
op-amp as that circuit does because of the increased loop gain and
accumulating phase shift.

Those are simulated waves.The scope captures are pretty similiar

though.
Yes I think your right. I had it before so it was nice and smooth
after the laod transient.Unfourtanetly I forgot the RC values. Theres
about fifty loose caps and resistors from ecperimenting on my bench
I'm sure I'll get lucky.