S
Srinivasan Venkataramanan
Guest
Hi,
My VHDL is little rusty by now. I'm thinking about direct entity
instantiation feature in VHDL-93 against lengthier component declarations.
I'm trying to see if there is still a technical need to declare components -
given that VHDL-93 has direct entity instantiation, why would you use
component declarations? I believe there is a value addition to declare
components - they can serve as sort of header files that define the
interface across blocks, but I would put that as more of a methodology than
core language. In other words: Is there any thing in the language sense that
can be done via component declaration that can't be achieved using direct
entity instantiation?
Thanks
Srini
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
My VHDL is little rusty by now. I'm thinking about direct entity
instantiation feature in VHDL-93 against lengthier component declarations.
I'm trying to see if there is still a technical need to declare components -
given that VHDL-93 has direct entity instantiation, why would you use
component declarations? I believe there is a value addition to declare
components - they can serve as sort of header files that define the
interface across blocks, but I would put that as more of a methodology than
core language. In other words: Is there any thing in the language sense that
can be done via component declaration that can't be achieved using direct
entity instantiation?
Thanks
Srini
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned