Do you need delta cycles

Hi,

I am playing around with writing a toy vhdl/verilog like language and
as part of it I want to emit c-code.

The language only allows synthesizable logic to be described and forces
you to decide what sort of variable you declare - combinatorial or
registered. There are no always blocks with sensitivity lists nor any
# style delays. Everything is either combinatorial or updated by an
implicit clock.

I have a verilog generator which seems to work but C is a little
harder. In C I have to deal with sensitivity lists and delta cycles
somehow, particularly for combinational logic. I was wondering if it
is possible to do so without having to run the process multiple times
until the values "settle". I have written some logic which orders the
signal assignments and as far as I can see this should be sufficient,
but I am just not convinced there isn't a simple counter example I
haven't considered.

For example;

always @ *
begin
b = a + 5;
a = c;
end

Swap the above two assignments and you could evaluate this in one pass.

Cheers,

Andy

 

[naren]

Hi Andy,
If these statements were to be in different "modules" or "files" will
your scheduling algorithm take care??
Actually what you are trying is theoritically possible (from my
understanding), if the complete design is Synchronous (which looks like
your language forces). So what you have to take care is that your
scheduling algorithm should be able to work across modules & files
et.al.
Thanks & Regards,
Naren.
TooMuch Semiconductor Solutions.
Specialising in Verification Technologies.

 

Hi Naren,

Thanks for your comments. I had hoped that was the case.

Modules I was going to deal with by essentially flattening design.
Nice and simple but I guess it could take some time for largish
designs.

Cheers,

Andy

 

What you are talking about is "levelizing" the code, which is a
standard technique for cycle simulation. It works as long as there are
no combinational loops in the code.