DO file creation

R

rsk

Guest
Hi Friends,

Can anyone help me in writing out a do file for simulating verilog files
dff.v and dff_tb.v.

Its very urgent.

Thanks,
Rs
 
On Apr 12, 6:31 pm, "rsk" <krs_1...@yahoo.co.in> wrote:
Hi Friends,

Can anyone help me in writing out a do file for simulating verilog files
dff.v and dff_tb.v.

Its very urgent.

Thanks,
Rs
Which simulator? Why not read its documentaion? With VCS it is:

vcs dff.v and dff_tb.v -R

MTI:

vlog dff.v and dff_tb.v
vsim dff_tb

Better read the tool doc.

Regards
Ajeetha, CVC
www.noveldv.com
 
thanks ajeetha.But i know we have to use
vlib,vlog,vsim commands.But i want to know how do we can use them in case
of modelsim tool.
 
On Apr 18, 7:49 am, "rsk" <krs_1...@yahoo.co.in> wrote:
thanks ajeetha.But i know we have to use
vlib,vlog,vsim commands.But i want to know how do we can use them in case
of modelsim tool.
First, create library directory:

vlib work

Second, compile all verilog files:

vlog [-y lib_dir] [-v lib_file] source_file(s) (run "vlog -help" for
more options)

Third, run simulation.

Interactive sim: --------------------
vsim top_level_module(s)

Opens Modelsim gui.
From the command line, run commands such as:
add wave -r * (to add all signals to waveform window)
run -all (run time controled from verilog with $stop command) or:
run 1000 (specify run time from the command line)

Also, it is useful to write the number of useful tcl procedures into
the "do" file and source this file to the modelsim:
vsim -do "run.do" top_level_module(s)

batch sim: ------------------------
vsim -c -do "run -all; quit -f" top_level_module(s)


Regards,
-Alex
 

Welcome to EDABoard.com

Sponsor

Back
Top