DLL - Change in input frequency (CLKIN)

[Rajesh Murugesan]

Hi all,

In my design, DLL is used to multiply the input frequency at the
factor of 2. Since the input source clock is from the external PLL
(Generates 2 different frequency---Change in input frequency), a
manual reset is mandatory. When I tried to generate an INTERNAL SIGNAL
and mapped to the reset signal (RST) of the DLL, there were errors as
mentioned below:

ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The
possible
drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block rst_in with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.

Would the design implementation in FPGA allow the user to map an
internally generated reset signal to the reset signal of the DLL?

Tool: Xilinx ISE 6.2i

Device: Spartan XC2S200

Eagerly waiting for your suggestions..

Thanks in advance

Regards
Rajesh

 

[Tony Dean]

rajes_kumar@yahoo.com (Rajesh Murugesan) wrote in message news:<5b293f11.0405172336.39ea9f62@posting.google.com>...

Hi all,

In my design, DLL is used to multiply the input frequency at the
factor of 2. Since the input source clock is from the external PLL
(Generates 2 different frequency---Change in input frequency), a
manual reset is mandatory. When I tried to generate an INTERNAL SIGNAL
and mapped to the reset signal (RST) of the DLL, there were errors as
mentioned below:

ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The
possible
drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block rst_in with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.

Would the design implementation in FPGA allow the user to map an
internally generated reset signal to the reset signal of the DLL?

Tool: Xilinx ISE 6.2i

Device: Spartan XC2S200

Eagerly waiting for your suggestions..

Thanks in advance

Regards
Rajesh

I have the same requirement and have successfully generated a reset
signal for the CLKDLL, so I know it can be done. It looks something
like this:

dll : CLKDLL port map (
CLKIN => clk,
CLKFB => clkfb,
RST => dll_reset,
etc.
);

dll_reset <= error1 OR error2; -- error1, error2 generated by internal
logic

Good luck!
-td

 

[Symon]

Hi Rajesh,
I wonder if net 'rst_in' has multiple drivers? Have you checked your code to
make sure you're not driving it to '0' as well as driving it from your
input?
cheers, Syms.
"Rajesh Murugesan" <rajes_kumar@yahoo.com> wrote in message
news:5b293f11.0405172336.39ea9f62@posting.google.com...

ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The
possible
drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block rst_in with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.

 

[Rajesh Murugesan]

td@emu.com (Tony Dean) wrote in message news:<33aa9b10.0405181256.7895fada@posting.google.com>...

I have the same requirement and have successfully generated a reset
signal for the CLKDLL, so I know it can be done. It looks something
like this:

dll : CLKDLL port map (
CLKIN => clk,
CLKFB => clkfb,
RST => dll_reset,
etc.
);

dll_reset <= error1 OR error2; -- error1, error2 generated by internal
logic

Good luck!
-td

Hi

Thanks a lot.. I tried to generate a reset signal for the DLL from the
above mentioned logic and I found the same errors as it was before.

I guess its not because of the bad logic and I am not sure whether the
rest of the design (apart from the using DLL) has logical errors. I
have been using Xilinx ISE 6.2i and the service pack of the current
version is updated as well.

Also. I have gotten new warnings...

********************

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:488 - Attribute value "LVCMOS25" is not an accepted
value for
attribute "IOSTANDARD" on "Clock_x4_rstpad".
WARNING:NgdBuild:488 - Attribute value "LVCMOS25" is not an accepted
value for
attribute "IOSTANDARD" on "mod_clk_x2_rstpad".
WARNING:NgdBuild:488 - Attribute value "LVCMOS25" is not an accepted
value for
attribute "IOSTANDARD" on "Clock_x4_clkpad".
WARNING:NgdBuild:488 - Attribute value "LVCMOS25" is not an accepted
value for
attribute "IOSTANDARD" on "mod_clk_x2_clk40_pad".

*******************

The error list also denote me that the reset signal has illegal
connection and in the .ngr file, I see the illegal connection that I
havent mentioned in the design.

Eagerly waiting for ur suggestions...

Thanks in advance..

grüss

Rajesh

 

[Rajesh Murugesan]

rajes_kumar@yahoo.com (Rajesh Murugesan) wrote in message news:<5b293f11.0405241143.1d54258e@posting.google.com>...

td@emu.com (Tony Dean) wrote in message news:<33aa9b10.0405181256.7895fada@posting.google.com>...

I have the same requirement and have successfully generated a reset
signal for the CLKDLL, so I know it can be done. It looks something
like this:

dll : CLKDLL port map (
CLKIN => clk,
CLKFB => clkfb,
RST => dll_reset,
etc.
);

dll_reset <= error1 OR error2; -- error1, error2 generated by internal
logic

Good luck!
-td

******
Hi

I tried to generate the reset signal for the CLKDLL, where the reset
signal is generated by internal logic (thnx to Tony!!!).Still I get
errors when I tried to implement the design. If i dont use the reset
pin of the DLL(ie, when the reset pin is tied to ground), there are no
errors. Since there is change in input frequency, manual reset is
mandatory. Device: Spartan II

To Tony: Did you use a change in input frequency and if so..how did
you activate and de-activate the reset signal when there is a change
in input frequency?

CODE:
rst_a, rst_b : signal
f_done_prog, f_start_prog_pll : input
rst_out: output

<<if modu_clk'event and modu_clk = '1' then
if (div16_clk_counter(3)='0' and sclk_div16='1') then
case reset_status is
when rst_boot =>
rst_out <= rst_a OR rst_b;
reset_status <= rst_0;
when rst_0 =>
if f_done_prog_pll ='1' then
rst_a <= '0';
rst_b <= '0';
reset_status <= rst_1;
end if;
when rst_1 =>
rst_out <= rst_a OR rst_b;
reset_status <= rst_2;
when rst_2 =>
if f_start_prog_pll = '0' then
rst_b <= '1';
reset_status <= rst_3;
end if;
when rst_3 =>
rst_out <= rst_a OR rst_b;
reset_status <= rst_0;
end case;


dll : CLKDLL port map (
CLKIN => clk,
CLKFB => clkfb,
RST => rst_out,
etc.
);
**************************
ERRORS:
ERROR:NgdBuild:455 - logical net 'rst_rst_out' has multiple drivers.
The
possible drivers causing this are:
pin Q on block rst_rst_out with type FDE,
pin PAD on block rst_rst_out.PAD with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_rst_out' has illegal
connection.
Possible pins causing this are:
pin Q on block rst_rst_out with type FDE,
pin I0 on block rst__n000812_SW0 with type LUT3

Also..Checked the RTL-schematic and could not find any multiple
drivers or an illegal connection. Am I doing wrond anywhere.
Suggestions please!!!

Thanks in advance.

Regards
Rajesh

 

[lee news]

Yes this is possible.

See our downloadable design examples, specifically the clocks file, I haves
assumed Xilinx and XST flow etc.

This does more than what you want, as it synchronises some external SDRAM
memorys too.

rs_sys comes from an input buffer (IBUF) etc.

Good Luck


----------------------------------------------------------------------------
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--
-- The ExpressIP Licence Agreement is to be used over and above all other
agreements.
--
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
----------
--



LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


-- synthesis translate_off
LIBRARY unisim;
USE unisim.ALL;
-- synthesis translate_on


ENTITY ExpressIP_clks IS
PORT(
ra_sys : IN STD_LOGIC
; -- System asynchronous reset.
cki_sys : IN STD_LOGIC
; -- 27MHz raw clock in from osc.
ckr_sys : OUT STD_LOGIC
; -- 54MHZ (x2) System clock output for use inside FPGA, clock tree output.

cki_capt : IN STD_LOGIC
; -- capture clock.
ckr_capt : OUT STD_LOGIC
; -- capture clock.
ckr_capt_dir : OUT STD_LOGIC
; -- capture clock direct.


cko_54MHz_1 : OUT STD_LOGIC
; -- 54MHZ (x2) System clock output for use outside FPGA, with sdrams.
cki_54MHz_1 : IN STD_LOGIC
; -- feedback version of cko_54MHz_1 for DLL in EpressIP_clks.vhd, used to
synchronise the clocks.

cko_54MHz_2 : OUT STD_LOGIC
; -- 54MHZ (x2) System clock output for use outside FPGA, with sdrams.
cki_54MHz_2 : IN STD_LOGIC
; -- feedback version of cko_54MHz_2 for DLL in EpressIP_clks.vhd, used to
synchronise the clocks.

op_dlls_capt_locked : OUT STD_LOGIC
; -- indicates the DLL's are settled
op_dlls_locked_extd : OUT STD_LOGIC
; -- indicates the DLL's are settled but delayed so that the pulse can be
used in a state machine etc.
op_dlls_locked : OUT
-- indicates the DLL's are settled.
);
END ExpressIP_clks;

ARCHITECTURE asic OF ExpressIP_clks IS


COMPONENT CLKDLL
PORT (clkin, clkfb, rst : IN STD_LOGIC;
clk0, clk90, clk180, clk270, clk2x, clkdv, locked : OUT STD_LOGIC);
END COMPONENT;

COMPONENT IBUFG
PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC);
END COMPONENT;

COMPONENT BUFG
PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC);
END COMPONENT;

COMPONENT OBUF
PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC);
END COMPONENT;


COMPONENT SRL16E
PORT (D : IN STD_LOGIC ;
CLK : IN STD_LOGIC ;
Q : OUT STD_LOGIC ;
CE : IN STD_LOGIC ;
A3 : IN STD_LOGIC ;
A2 : IN STD_LOGIC ;
A1 : IN STD_LOGIC ;
A0 : IN STD_LOGIC
);
END COMPONENT;

SIGNAL s_ra_sys : STD_LOGIC
;

SIGNAL s_logic1 : STD_LOGIC := '1'
;
SIGNAL s_clk_in_ibuf : STD_LOGIC
;
SIGNAL s_clk_fb_ibuf : STD_LOGIC
;
SIGNAL s_clk_108_ibuf : STD_LOGIC
;
SIGNAL s_clk_dllx2_ext : STD_LOGIC
;
SIGNAL s_dll_locked_ext : STD_LOGIC
;
SIGNAL s_cko_54MHz : STD_LOGIC
;
SIGNAL s_clk_dllx2_int : STD_LOGIC
;
SIGNAL s_dll_locked_int : STD_LOGIC
;
SIGNAL s_clk_a_out : STD_LOGIC
;
SIGNAL s_clk_dllx4_int : STD_LOGIC
;
SIGNAL s_clk_108_out : STD_LOGIC
;
SIGNAL s_clk_dllx4_ext : STD_LOGIC
;
SIGNAL s_op_dlls_locked : STD_LOGIC
;
SIGNAL s_dll_locked_int_dly : STD_LOGIC
;
SIGNAL s_dll_locked_int_dly_inv : STD_LOGIC
;
SIGNAL s_dll_locked_ext_dly : STD_LOGIC
;
SIGNAL s_dll_locked_ext_dly_inv : STD_LOGIC
;
SIGNAL s_op_dlls_locked_extd : STD_LOGIC
;
SIGNAL s_op_dlls_locked_extdd : STD_LOGIC
;
SIGNAL s_dll_locked_108int : STD_LOGIC
;
SIGNAL s_read_addr : STD_LOGIC_VECTOR(3 DOWNTO 0)
;


SIGNAL s_clk_capt_ibuf : STD_LOGIC
;
SIGNAL s_clk_capt_int : STD_LOGIC
;
SIGNAL s_clk_capt_out : STD_LOGIC
;
SIGNAL s_dll_locked_capt : STD_LOGIC
;


BEGIN

s_ra_sys <= NOT(ra_sys) ;

ibufg_i0 : IBUFG
PORT MAP (
I => cki_sys ,
O => s_clk_in_ibuf
);

ibufg_i1 : IBUFG
PORT MAP (
I => cki_54MHz_1 ,
O => s_clk_fb_ibuf
);


ibufg_i2 : IBUFG
PORT MAP (
I => cki_54MHz_2 ,
O => s_clk_108_ibuf
);

clkdll_i0 : CLKDLL
PORT MAP (
CLKIN => s_clk_in_ibuf ,
CLKFB => s_clk_a_out ,
RST => s_ra_sys ,
CLK2X => s_clk_dllx2_int ,
clk0 => OPEN ,
clk90 => OPEN ,
clk180 => OPEN ,
clk270 => OPEN ,
clkdv => OPEN ,
LOCKED => s_dll_locked_int
);

bufg0 : BUFG
PORT MAP (
I => s_clk_dllx2_int ,
O => s_clk_a_out
);

ckr_sys <= s_clk_a_out ;


ExpressIP_pipe_srl16_1_i0 : srl16e
PORT MAP (
CLK => s_clk_in_ibuf ,
D => s_dll_locked_int ,
Q => s_dll_locked_int_dly ,
CE => s_logic1 ,
A3 => s_read_addr(3) ,
A2 => s_read_addr(2) ,
A1 => s_read_addr(1) ,
A0 => s_read_addr(0)
);


s_dll_locked_int_dly_inv <= NOT(s_dll_locked_int_dly) ;

clkdll_i1 : CLKDLL
PORT MAP (
CLKIN => s_clk_a_out ,
CLKFB => s_clk_fb_ibuf ,
RST => s_dll_locked_int_dly_inv ,
CLK2X => s_clk_dllx4_ext ,
clk0 => s_clk_dllx2_ext ,
clk90 => OPEN ,
clk180 => OPEN ,
clk270 => OPEN ,
clkdv => OPEN ,
LOCKED => s_dll_locked_ext
);

obuf_i1 : OBUF
PORT MAP (
I => s_clk_dllx2_ext ,
O => s_cko_54MHz
);

cko_54MHz_1 <= s_cko_54MHz ;


ExpressIP_pipe_srl16_1_i1 : srl16e
PORT MAP (
CLK => s_clk_in_ibuf ,
D => s_dll_locked_ext ,
Q => s_dll_locked_ext_dly ,
CE => s_logic1 ,
A3 => s_read_addr(3) ,
A2 => s_read_addr(2) ,
A1 => s_read_addr(1) ,
A0 => s_read_addr(0)
);


s_dll_locked_ext_dly_inv <= NOT(s_dll_locked_ext_dly) ;

clkdll_i2 : CLKDLL
PORT MAP (
CLKIN => s_clk_a_out ,
CLKFB => s_clk_108_ibuf ,
RST => s_dll_locked_ext_dly_inv ,
CLK2X => OPEN ,
clk0 => s_clk_dllx4_int ,
clk90 => OPEN ,
clk180 => OPEN ,
clk270 => OPEN ,
clkdv => OPEN ,
LOCKED => s_dll_locked_108int
);


obuf1 : OBUF
PORT MAP (
I => s_clk_dllx4_int ,
O => s_clk_108_out
);

cko_54MHz_2 <= s_clk_108_out ;


s_op_dlls_locked <= s_dll_locked_ext;

op_dlls_locked <= s_op_dlls_locked_extd ;


ExpressIP_pipe_srl16_1_i2 : srl16e
PORT MAP (
CLK => s_clk_in_ibuf ,
D => s_op_dlls_locked ,
Q => s_op_dlls_locked_extd ,
CE => s_logic1 ,
A3 => s_read_addr(3) ,
A2 => s_read_addr(2) ,
A1 => s_read_addr(1) ,
A0 => s_read_addr(0)
);


s_read_addr <= (OTHERS => '1' ) ;

ExpressIP_pipe_srl16_1_i3 : srl16e
PORT MAP (
CLK => s_clk_in_ibuf ,
D => s_op_dlls_locked_extd ,
Q => s_op_dlls_locked_extdd ,
CE => s_logic1 ,
A3 => s_read_addr(3) ,
A2 => s_read_addr(2) ,
A1 => s_read_addr(1) ,
A0 => s_read_addr(0)
);




op_dlls_locked_extd <= s_op_dlls_locked_extdd ;





-- capture clock

ibufg_i3 : IBUFG
PORT MAP (
I => cki_capt ,
O => s_clk_capt_ibuf
);


clkdll_i3 : CLKDLL
PORT MAP (
CLKIN => s_clk_capt_ibuf ,
CLKFB => s_clk_capt_out ,
RST => s_ra_sys ,
CLK2X => OPEN ,
clk0 => s_clk_capt_int ,
clk90 => OPEN ,
clk180 => OPEN ,
clk270 => OPEN ,
clkdv => OPEN ,
LOCKED => s_dll_locked_capt
);

bufg1 : BUFG
PORT MAP (
I => s_clk_capt_int ,
O => s_clk_capt_out
);


ckr_capt <= s_clk_capt_out ;
ckr_capt_dir <= s_clk_capt_ibuf ;

op_dlls_capt_locked <= s_dll_locked_capt ; -- indicates
the DLL's are settled





END asic;




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"Rajesh Murugesan" <rajes_kumar@yahoo.com> wrote in message
news:5b293f11.0405172336.39ea9f62@posting.google.com...

Hi all,

In my design, DLL is used to multiply the input frequency at the
factor of 2. Since the input source clock is from the external PLL
(Generates 2 different frequency---Change in input frequency), a
manual reset is mandatory. When I tried to generate an INTERNAL SIGNAL
and mapped to the reset signal (RST) of the DLL, there were errors as
mentioned below:

ERROR:NgdBuild:455 - logical net 'rst_in' has multiple drivers. The
possible
drivers causing this are:
pin G on block XST_GND with type GND,
pin PAD on block rst_in with type PAD
ERROR:NgdBuild:466 - input pad net 'rst_in' has illegal connection.

Would the design implementation in FPGA allow the user to map an
internally generated reset signal to the reset signal of the DLL?

Tool: Xilinx ISE 6.2i

Device: Spartan XC2S200

Eagerly waiting for your suggestions..

Thanks in advance

Regards
Rajesh