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Replace_latter8717_with_manorsway wrote:
remember log division from schoool, now try that in base 2!
Yes.
And then develop a hardware design that can do that...
When this is done, it's a small step to describe it in VHDL.
Regards,
Mario
"Ketan" <ketone007sa@yahoo.com> wrote in message
news:cf47f3cc.0307042130.1eec1888@posting.google.com...
hello there
i am relatively new to VHDL..this might sound simple
any ideas how to carry out division (floating point) in VHDL??
--
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Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
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For a few seconds I considered that you meant subtracting logs to doSorry I meant LONG division not LOG
"Replace_latter8717_with_manorsway" <david@latter8717.freeserve.co.uk> wrote
in message news:behtt2$j78$1@newsg1.svr.pol.co.uk...
Sorry I meant LONG division not LOG
For a few seconds I considered that you meant subtracting logs to do
division. But then I figured it out. I don't think subtracting logs and
then antilog is likely to be a very good way in FPGA.
-- glen
hello there
i am relatively new to VHDL..this might sound simple
any ideas how to carry out division (floating point) in VHDL??
Yes.remember log division from schoool, now try that in base 2!
--"Ketan" <ketone007sa@yahoo.com> wrote in message
news:cf47f3cc.0307042130.1eec1888@posting.google.com...
hello there
i am relatively new to VHDL..this might sound simple
any ideas how to carry out division (floating point) in VHDL??