Division in Xilinx

[Andy]

Hi all,
I am trying to implement a small ALU module using the Xilinx ISE web
pack and the simulator is Silos.
When I try to synthesize this design, it gives me an error for the
division. I have implemented division directly, i.e. out <= A / B;
All I know is this is a pretty inefficient way of doing it but was not
expecting errors.

Any tips or pointers will be very helpful.

Thanks,
Andy

 

[Jon Beniston]

bayou1221@yahoo.com (Andy) wrote in message news:<cbff8633.0406222001.6d2a0e93@posting.google.com>...

Hi all,
I am trying to implement a small ALU module using the Xilinx ISE web
pack and the simulator is Silos.
When I try to synthesize this design, it gives me an error for the
division. I have implemented division directly, i.e. out <= A / B;
All I know is this is a pretty inefficient way of doing it but was not
expecting errors.

/ is not a synthesizable operator.

Cheers,
JonB

 

[John_H]

If you want division and don't have a Virtex4 (?!) you'll have to do the
division yourself in hardware or in software.

Small microcontrollers have rarely had division in their ALUs with the
software division supported by routines with a series of add/subtract,
rotate through carry, and shift operations.

"Andy" <bayou1221@yahoo.com> wrote in message
news:cbff8633.0406222001.6d2a0e93@posting.google.com...

Hi all,
I am trying to implement a small ALU module using the Xilinx ISE web
pack and the simulator is Silos.
When I try to synthesize this design, it gives me an error for the
division. I have implemented division directly, i.e. out <= A / B;
All I know is this is a pretty inefficient way of doing it but was not
expecting errors.

Any tips or pointers will be very helpful.

Thanks,
Andy

 

[Symon]

"Jon Beniston" <jon@beniston.com> wrote in message
news:e87b9ce8.0406230554.1198a15a@posting.google.com...

bayou1221@yahoo.com (Andy) wrote in message
news:<cbff8633.0406222001.6d2a0e93@posting.google.com>...

/ is not a synthesizable operator.

Oh yes it (sort of) is! From the Synplify reference manual:-

Operators /, mod, and rem are supported for compile-time constants or
when the right argument is a power of 2.

Cheers, Symon 'Pedant' Brewer.

 

[Jonas Floden]

Compile-time constants would be something like,
out <= 11 / 7;
where the compiler replaces it whit a constant like
out <= 1.5....;

and the other case when the right argument is a power of 2 is something like
out <= B / 8;
which would be replace whit a shift right
out <= B >> 3;

neither of these examples would result in any division hardware

But your example
out <= A / B;

doesn't fit either of these. If this is what you really need you would
have to implement your own division.

Hope this helps

// Jonas

 

[Kelvin]

Lookup table is the answer...
FPGA-based designs usually have abundant LUTs...

Kelvin




"Andy" <bayou1221@yahoo.com> wrote in message
news:cbff8633.0406222001.6d2a0e93@posting.google.com...

Hi all,
I am trying to implement a small ALU module using the Xilinx ISE web
pack and the simulator is Silos.
When I try to synthesize this design, it gives me an error for the
division. I have implemented division directly, i.e. out <= A / B;
All I know is this is a pretty inefficient way of doing it but was not
expecting errors.

Any tips or pointers will be very helpful.

Thanks,
Andy