Divide clock by 4/5 in Spartan 3A?

T

Tim Wescott

Guest
Part: Xilinx Spartan 3A DSP
Problem:
(a) My customer has a 100MHz clock, my test board has a 125MHz clock.
(b) I'm a systems guy who knows enough FPGA designs to turn math
into HDL, but I'm no FPGA guru.

Solution?

The customer suggested just using Xilinx's DCM wizard to divide the
clock by 4/5 -- but I don't see where that can be done (I'm using ISE
11.5, to match my customer's set up).

So -- is there a way to get a clean 100MHz clock from a 125MHz clock
with the DCM hardware?

I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
then 3 then 2 etc -- but that's weird, and besides I'd still need
everything to be good to 8ns rather than 10ns as with a 100MHz clock.

(Or I could just jigger a bunch of constants, which is looking more
attractive by the second).

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Divide clock by 5/4. Oops.

This is why I make a better engineer than the fighter pilot I wanted to
be. If you're doing design and you flip a few digits, then you check
back later and fix -- no problem. OTOH, get your targeting system
locked on a bogey, push the big red button, find out it was a transport
full of brass or civilians -- oopsie, no second tries there!

On 09/08/2010 12:03 PM, Tim Wescott wrote:
Part: Xilinx Spartan 3A DSP
Problem:
(a) My customer has a 100MHz clock, my test board has a 125MHz clock.
(b) I'm a systems guy who knows enough FPGA designs to turn math
into HDL, but I'm no FPGA guru.

Solution?

The customer suggested just using Xilinx's DCM wizard to divide the
clock by 4/5 -- but I don't see where that can be done (I'm using ISE
11.5, to match my customer's set up).

So -- is there a way to get a clean 100MHz clock from a 125MHz clock
with the DCM hardware?

I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
then 3 then 2 etc -- but that's weird, and besides I'd still need
everything to be good to 8ns rather than 10ns as with a 100MHz clock.

(Or I could just jigger a bunch of constants, which is looking more
attractive by the second).
Click to expand...

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Tim Wescott <tim@seemywebsite.com> wrote:
Divide clock by 5/4. Oops.
Click to expand...
When I read the previous post, I was wondering if it would be
more usual to specify as a multiply than divide. That is,
multiply by 4/5 or divide by 5/4.

In the case of using a counter to divide by an integer, divide
makes sense. Also, some time ago Peter Alfke gave a design
for a divide by 2.5 using FF's circuit. I almost thought that
was what you were asking about, but then I saw the 4.

This is why I make a better engineer than the fighter pilot I wanted to
be. If you're doing design and you flip a few digits, then you check
back later and fix -- no problem. OTOH, get your targeting system
locked on a bogey, push the big red button, find out it was a transport
full of brass or civilians -- oopsie, no second tries there!
Click to expand...
-- glen
 
On Sep 8, 12:03 pm, Tim Wescott <t...@seemywebsite.com> wrote:
Part: Xilinx Spartan 3A DSP
Problem:
  (a) My customer has a 100MHz clock, my test board has a 125MHz clock.
  (b) I'm a systems guy who knows enough FPGA designs to turn math
      into HDL, but I'm no FPGA guru.

Solution?

The customer suggested just using Xilinx's DCM wizard to divide the
clock by 4/5 -- but I don't see where that can be done (I'm using ISE
11.5, to match my customer's set up).

So -- is there a way to get a clean 100MHz clock from a 125MHz clock
with the DCM hardware?

I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
then 3 then 2 etc -- but that's weird, and besides I'd still need
everything to be good to 8ns rather than 10ns as with a 100MHz clock.

(Or I could just jigger a bunch of constants, which is looking more
attractive by the second).

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details athttp://www.wescottdesign.com/actfes/actfes.html
Click to expand...
This is easy to do using the Coregen Spartan-3A DCM Wizard.

1) Start CoreGen
2) Create a new project that targets Spartan-3A DSP
3) Select FPGA Features -> Clocking -> Spartan-3A -> Single DCM_SP
core
4) Customize the core with your settings
- Select the CLKFX output
- Add 125 MHz as the CLKIN frequency
- Use the internal feedback mode
- Use Global buffers for clock outputs
- Add 100 MHz as the CLKFX output frequency and click Calculate
Values
- Click Finish to generate your HDL

Ed McGettigan
--
Xilinx Inc.
 
Thanks Ed -- that appears to do what I need.

Now if I can just get the _rest_ of it to work, I'll be fine!

On 09/08/2010 02:02 PM, Ed McGettigan wrote:
On Sep 8, 12:03 pm, Tim Wescott<t...@seemywebsite.com> wrote:
Part: Xilinx Spartan 3A DSP
Problem:
(a) My customer has a 100MHz clock, my test board has a 125MHz clock.
(b) I'm a systems guy who knows enough FPGA designs to turn math
into HDL, but I'm no FPGA guru.

Solution?

The customer suggested just using Xilinx's DCM wizard to divide the
clock by 4/5 -- but I don't see where that can be done (I'm using ISE
11.5, to match my customer's set up).

So -- is there a way to get a clean 100MHz clock from a 125MHz clock
with the DCM hardware?

I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
then 3 then 2 etc -- but that's weird, and besides I'd still need
everything to be good to 8ns rather than 10ns as with a 100MHz clock.

(Or I could just jigger a bunch of constants, which is looking more
attractive by the second).

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details athttp://www.wescottdesign.com/actfes/actfes.html

This is easy to do using the Coregen Spartan-3A DCM Wizard.

1) Start CoreGen
2) Create a new project that targets Spartan-3A DSP
3) Select FPGA Features -> Clocking -> Spartan-3A -> Single DCM_SP
core
4) Customize the core with your settings
- Select the CLKFX output
- Add 125 MHz as the CLKIN frequency
- Use the internal feedback mode
- Use Global buffers for clock outputs
- Add 100 MHz as the CLKFX output frequency and click Calculate
Values
- Click Finish to generate your HDL

Ed McGettigan
--
Xilinx Inc.
Click to expand...

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
On 9 Sep., 01:51, Tim Wescott <t...@seemywebsite.com> wrote:
Thanks Ed -- that appears to do what I need.

Now if I can just get the _rest_ of it to work, I'll be fine!
Click to expand...
Just select the "Remaining Project Functionality Block 12.1.4" from
coregen and choose the required settings.
I do not know if Spartan-3A is supported for that core...

;-)

Kolja
 
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