divide by on spartan3?

[Theron Hicks]

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

 

[Ray Andraka]

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Theron Hicks (Terry)]

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[John]

"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<bkcrmn$iah$1@msunews.cl.msu.edu>...

Hello,
in Spartan3
what is the fastest I can do a 16bit divide (unsigned) > Thanks,
Theron Hicks

Perhaps try table lookup using blockram, followed by Newton-Raphson
iteration..see for example:
http://citeseer.nj.nec.com/oberman95analysis.html
HTH
John

 

[Peter Alfke]

Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
<10 ns .
I think you can use this in a successive approximation loop with max 14
or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
seems like a "piece-of-cake" to me.
Peter Alfke

"Theron Hicks (Terry)" wrote:

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Peter Alfke]

Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
<10 ns .
I think you can use this in a successive approximation loop with max 14
or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
seems like a "piece-of-cake" to me.
Peter Alfke

"Theron Hicks (Terry)" wrote:

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Glen Herrmannsfeldt]

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F6A547B.D4673C29@xilinx.com...

Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
10 ns .
I think you can use this in a successive approximation loop with max 14
or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
seems like a "piece-of-cake" to me.
Peter Alfke

Even more, if I understand the application, it will be reading a slowly
varying resistance. Using the previous result as the new approximation, and
assuming reasonable rates of change, it should be able to generate a new
result each cycle, after the first 16 cycles.

-- glen

 

[Hal Murray]

Even more, if I understand the application, it will be reading a slowly
varying resistance. Using the previous result as the new approximation, and
assuming reasonable rates of change, it should be able to generate a new
result each cycle, after the first 16 cycles.

It may be even simpler than that.

You might be able to avoid the divide and come up with some
kludge heuristics, say table lookup on the difference between
the current reading and the previous reading and add/sub that
the the running answer.

Something like that can easily get you lots of bits of output
and/or gives you a place to put in a PLL filter. (I'm guessing
this is some sort of PLL.)


I still don't understand the big picture. It takes two numbers to
do a divide, but the description only mentioned one A/D. Where does
the other number come from? Which one is on top?

[obvious comments about multiply by inverse if you can]

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Theron Hicks]

I will try again...

Two resistors in series. Top resistor is fixed value (40 ohms). Bottom
resistor is a very small (5 micron dia) tungsten wire. (Resistance is RT.
RT is held at 1.7 time the ambient temperature resistance (RA) of the
tungsten by I^2*R.) We are trying to maintain a constant and elevated
temperature in the tungsten wire. This is accomplished by maintaining a
constant resistance in the tungsten wire. The temperature of the tungsten
varies because of airflow past the tungsten and I^2*R heating of the
tungsten. This heating is provided by a D/A who's output is connected to
the 40 ohm resistor. Call this V1. The voltage drop across the tungsten is
measured via the A/D. Call this V2. The desired ressitance of the tungsten
is RD. RT can be calculated using V2/V1=RT/(RT+40). The error term
RT-(1.7*RA) is the input to a PID controller. The output of the PID is
(effectively) V1. V1 can be used to calculate the velocity of the airflow
past the tungsten wire. The current (analog wheatstone bridge based) system
has a cutoff frequency of about 35KHz. My simulation of the system using
Matlab indicates that a digital control loop based system can respond at in
excess of 100KHz even allowing for the time necessary to calculate RD using
a division and allowing for a 460ns A/D converter. If I can get up to
250KHz, the market is wide open. Small quantities but high prices.
Curently the analog system goes for $5 to $10k US per cahnnel. Even at
100KHz frequency response, I can sell them very easily at $2000 (US) per
channel. Does that make a little more sense? The system is similar to the
Pulse Width Modulated Constant Temperature Anemometer discribed in the first
link below. The PWM circuitry is replaced with a digital PID using an A/D
and a D/A converter. Alternatively, look at US patent 5,654,507.

These links may (or may not) help clarify the issue.

http://www.iop.org/EJ/abstract/0957-0233/14/3/302/
http://www.iop.org/EJ/abstract/0957-0233/9/5/006

Thanks,
Theron Hicks






"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vml5vnjsq83m28@corp.supernews.com...

Even more, if I understand the application, it will be reading a slowly
varying resistance. Using the previous result as the new approximation,
and
assuming reasonable rates of change, it should be able to generate a new
result each cycle, after the first 16 cycles.

It may be even simpler than that.

You might be able to avoid the divide and come up with some
kludge heuristics, say table lookup on the difference between
the current reading and the previous reading and add/sub that
the the running answer.

Something like that can easily get you lots of bits of output
and/or gives you a place to put in a PLL filter. (I'm guessing
this is some sort of PLL.)


I still don't understand the big picture. It takes two numbers to
do a divide, but the description only mentioned one A/D. Where does
the other number come from? Which one is on top?

[obvious comments about multiply by inverse if you can]

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
commercial e-mail to my suespammers.org address or any of my other
addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[John]

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6A547B.D4673C29@xilinx.com>...

Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
10 ns .
I think you can use this in a successive approximation loop with max 14
or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
seems like a "piece-of-cake" to me.
Peter Alfke

(See my parallel post...I have to use Google for news posts, so I can't

put this after the other one...)
Ooops...my mistake, N-R requires _two_ multiplies per iteration. So,
balancing multipliers and block rams, use three block rams in parallel
to do 1st approximation using 12 MSBs of denominator, D. Depending on
range of the denominator, this should give a result accurate to at least
9 bits. One iteration of N-R gives 18 bits.
OK, for those who don't want to go to the literature,
N-R iteration for 1/D is:
X[i+1] = X * (2 - D * X)

A little expensive (three block rams organized as 12addr x 4bits, and
their associated multipliers), but fast...one cycle, plus combintorial
delays.
Regards,
John

"Theron Hicks (Terry)" wrote:

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Peter Alfke]

Thanks, Theron.
There seem to be many different ( very different) ways to solve the
digital portion of your design, all offering better than the required
performance. Good luck.
As they say: Just do it! The various digital schemes may be a wash in
the larger realm of things...
Peter Alfke
========================
Theron Hicks wrote:

I will try again...

Two resistors in series. Top resistor is fixed value (40 ohms). Bottom
resistor is a very small (5 micron dia) tungsten wire. (Resistance is RT.
RT is held at 1.7 time the ambient temperature resistance (RA) of the
tungsten by I^2*R.) We are trying to maintain a constant and elevated
temperature in the tungsten wire. This is accomplished by maintaining a
constant resistance in the tungsten wire. The temperature of the tungsten
varies because of airflow past the tungsten and I^2*R heating of the
tungsten. This heating is provided by a D/A who's output is connected to
the 40 ohm resistor. Call this V1. The voltage drop across the tungsten is
measured via the A/D. Call this V2. The desired ressitance of the tungsten
is RD. RT can be calculated using V2/V1=RT/(RT+40). The error term
RT-(1.7*RA) is the input to a PID controller. The output of the PID is
(effectively) V1. V1 can be used to calculate the velocity of the airflow
past the tungsten wire. The current (analog wheatstone bridge based) system
has a cutoff frequency of about 35KHz. My simulation of the system using
Matlab indicates that a digital control loop based system can respond at in
excess of 100KHz even allowing for the time necessary to calculate RD using
a division and allowing for a 460ns A/D converter. If I can get up to
250KHz, the market is wide open. Small quantities but high prices.
Curently the analog system goes for $5 to $10k US per cahnnel. Even at
100KHz frequency response, I can sell them very easily at $2000 (US) per
channel. Does that make a little more sense? The system is similar to the
Pulse Width Modulated Constant Temperature Anemometer discribed in the first
link below. The PWM circuitry is replaced with a digital PID using an A/D
and a D/A converter. Alternatively, look at US patent 5,654,507.

These links may (or may not) help clarify the issue.

http://www.iop.org/EJ/abstract/0957-0233/14/3/302/
http://www.iop.org/EJ/abstract/0957-0233/9/5/006

Thanks,
Theron Hicks

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vml5vnjsq83m28@corp.supernews.com...
Even more, if I understand the application, it will be reading a slowly
varying resistance. Using the previous result as the new approximation,
and
assuming reasonable rates of change, it should be able to generate a new
result each cycle, after the first 16 cycles.

It may be even simpler than that.

You might be able to avoid the divide and come up with some
kludge heuristics, say table lookup on the difference between
the current reading and the previous reading and add/sub that
the the running answer.

Something like that can easily get you lots of bits of output
and/or gives you a place to put in a PLL filter. (I'm guessing
this is some sort of PLL.)


I still don't understand the big picture. It takes two numbers to
do a divide, but the description only mentioned one A/D. Where does
the other number come from? Which one is on top?

[obvious comments about multiply by inverse if you can]

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
commercial e-mail to my suespammers.org address or any of my other
addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[John_H]

16 cycles of compare/subtract can go pretty darned fast! You can do it
compact in a single stage with a shift register for the result (16 bit
suptractor, 16 bit registered mux). 16 clock cycles at 6ns per clock cycle
is very achievable. If you want to throw resources at it, you could do a
simple combinatorial divide. I got 81ns in the tiny Spartan-3 with a first
rough-cut, no attempts to make it fast.

"Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
news:3F6A4BF2.6D4F21A@egr.msu.edu...

Sorry Ray,
I meant to give a little more detail than I ended up with. The number
of
clock cycles per divide is not critical. I cannot accept any pipeline
delay, but
I am willing to wait a few clock cycles before I get a final result. I
basically
need to get a divide-by result as quickly as possible. The inputs are 2
16 bit
numbers and I need a minimum of 14 bits in the result. I would really
like to get
to 16 bits if possible. The resultant resistance (the quotient) is
subtracted
from the desired resistance. This difference serves as the input to a
very fast
PID controller. This controller serves to control the temperature of a
hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the
time delay
between requesting a quotient and the time when that quotient is valid
needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder
of the
PID control loop should take about 30ns. I want the division to be
substantially
faster than the sum of those two times if possible. As a maximum, it must
be
faster that 500ns. If it were much faster (~100ns) then I could look at
faster
A/D converters for an even higher system throughput when desired. I hope
this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can
compromise on
accuracy, a normalize -> look up -> denormalize might be the best
approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the
resistance
of a sensor. Because of the remainder of the circuit configuration,
this
must be done using a voltage divider. If I implement this in a
spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I
can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would
prefer to
stick with what I am most comfortable with (FPGAs). My intent is to
use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Theron Hicks]

John,
Thanks. That was the kind of answer I was anticipating. However, the
other ideas have given me some potentially better solutions to consider.
Thanks to everyone who provided an input. As Peter said, "There seem to be
many different ( very different) ways to solve the
digital portion of your design..."

Theron Hicks

"John_H" <johnhandwork@mail.com> wrote in message
news:BhHab.16$Kq4.10256@news-west.eli.net...

16 cycles of compare/subtract can go pretty darned fast! You can do it
compact in a single stage with a shift register for the result (16 bit
suptractor, 16 bit registered mux). 16 clock cycles at 6ns per clock
cycle
is very achievable. If you want to throw resources at it, you could do a
simple combinatorial divide. I got 81ns in the tiny Spartan-3 with a
first
rough-cut, no attempts to make it fast.

"Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
news:3F6A4BF2.6D4F21A@egr.msu.edu...
Sorry Ray,
I meant to give a little more detail than I ended up with. The
number
of
clock cycles per divide is not critical. I cannot accept any pipeline
delay, but
I am willing to wait a few clock cycles before I get a final result. I
basically
need to get a divide-by result as quickly as possible. The inputs are 2
16 bit
numbers and I need a minimum of 14 bits in the result. I would really
like to get
to 16 bits if possible. The resultant resistance (the quotient) is
subtracted
from the desired resistance. This difference serves as the input to a
very fast
PID controller. This controller serves to control the temperature of a
hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the
time delay
between requesting a quotient and the time when that quotient is valid
needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The
remainder
of the
PID control loop should take about 30ns. I want the division to be
substantially
faster than the sum of those two times if possible. As a maximum, it
must
be
faster that 500ns. If it were much faster (~100ns) then I could look at
faster
A/D converters for an even higher system throughput when desired. I
hope
this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock
rate.
You aren't going to get all of them at once, however if you can
compromise on
accuracy, a normalize -> look up -> denormalize might be the best
approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the
resistance
of a sensor. Because of the remainder of the circuit configuration,
this
must be done using a voltage divider. If I implement this in a
spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I
can do a
shift and subtract, but I would prefer something a little faster.
Any
suggestions? (I know I could go to a fast DSP but again, I would
prefer to
stick with what I am most comfortable with (FPGAs). My intent is to
use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ray Andraka]

Terry,

This sounds like an ideal application for delta-sigma converters, since your control
is really based on the deltas not on the absolute values. I'd have to work through
the design, but it seems like it would work.

The thought came about because the division could start before the A/D conversion was
complete if the partial results were available. The ADC, assuming a successive
approximation type, gets the most significnt bits first then improves the mesurement
by refining the lsbs. Division is inherently MSB first as well. You can see where I
am going here.

"Theron Hicks (Terry)" wrote:

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Tom Seim]

john.l.smith@titan.com (John) wrote in message news:<5b9931fd.0309181642.739c694b@posting.google.com>...

"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<bkcrmn$iah$1@msunews.cl.msu.edu>...
Hello,
in Spartan3
what is the fastest I can do a 16bit divide (unsigned) > Thanks,
Theron Hicks

Perhaps try table lookup using blockram, followed by Newton-Raphson
iteration..see for example:
http://citeseer.nj.nec.com/oberman95analysis.html
HTH
John

This may be helpful:
http://citeseer.nj.nec.com/rice98multiprecision.html

Tom

 

[John]

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6A547B.D4673C29@xilinx.com>...

Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
10 ns .
I think you can use this in a successive approximation loop with max 14
or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
seems like a "piece-of-cake" to me.
Peter Alfke

Hi Terry,
Peter's got the right idea...if latency is an issue,
elaborating on my other post:

N/D, with N and D both 16 bits...
From the description of the physics, it is probably the case
that the denominator will be limited in range, as the sensor
will have neither infinite or zero resistance. With that in
mind, two block rams in parallel may get you within 8 bits for
a first approximation to the result, using a table lookup on the
top 11 bits of D. After that, using one iteration of Newton-Raphson
(see the other reference I gave) gets you 16 bits for 1/D, using one
of the multipliers associated with one of the block rams. The other
multiplier brings N back into the picture.

Thus, a single cycle of delay through the block ram, plus
combinatorial delay through the adds/mult for the Newton-Raphson
iteration, plus combinatorial through the numerator multiplication.
I'm confused by the statement: "No pipeline delay, but a few clock
cycles are OK"? How do you distinguish a few clock cycles from a
pipeline delay?

Regards,
John

"Theron Hicks (Terry)" wrote:

Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.

Thanks,
Theron

Ray Andraka wrote:

You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.

Theron Hicks wrote:

Hello,
I have a project in mind where I would like to caclculate the resistance
of a sensor. Because of the remainder of the circuit configuration, this
must be done using a voltage divider. If I implement this in a spartan3,
what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
shift and subtract, but I would prefer something a little faster. Any
suggestions? (I know I could go to a fast DSP but again, I would prefer to
stick with what I am most comfortable with (FPGAs). My intent is to use the
smallest spartan3 if posible.
Thanks,
Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759