displaying signed values

[Srinivas]

Hi,
i'm declaring a register with signed values.
after processing the data,i want to display the signed values on the screen
Any suggestions on how to do this?

TIA,
Srinivas

 

[Andy Peters]

srinivaserj@gmail.com (Srinivas) wrote in message news:<18bc100b.0410281919.3340e97@posting.google.com>...

Hi,
i'm declaring a register with signed values.
after processing the data,i want to display the signed values on the screen
Any suggestions on how to do this?

reg signed [FOOMSB:0];

$display("Foo is %d", foo);

-a

 

[Srinivas]

Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0410291311.1120a768@posting.google.com>...

srinivaserj@gmail.com (Srinivas) wrote in message news:<18bc100b.0410281919.3340e97@posting.google.com>...
Hi,
i'm declaring a register with signed values.
after processing the data,i want to display the signed values on the screen
Any suggestions on how to do this?

reg signed [FOOMSB:0];

$display("Foo is %d", foo);

-a

HI andy,
thanks for the suggestion.But this doesn't work.
I, guess , am looking for a more roundabout way of printing negative
numbers using display or any other print command.

Rgds,
Srinivas

 

[Steven Sharp]

srinivaserj@gmail.com (Srinivas) wrote in message news:<18bc100b.0411010045.15cec289@posting.google.com>...

Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0410291311.1120a768@posting.google.com>...

reg signed [FOOMSB:0] foo; //fixed typo here

$display("Foo is %d", foo);

thanks for the suggestion.But this doesn't work.

I assume that your tool accepts the "signed" qualifier. If
not, then it isn't Verilog-2001 compliant, and you can
probably forget about displaying in signed format.

I checked the Verilog-2001 LRM and didn't find anything that
specified that %d must print signed values in signed format.
However, I believe that all of the leading tools do, so that
is at least the de facto standard behavior. I would report
this as a bug to your simulator supplier.

If your simulator doesn't do this already, then you have no
way of doing it with $display. You would have to implement
your own print formatting, in Verilog or PLI. Not something
you want to do.