Displaying at less that the time_unit...

[EdA]

% cat junk.v
`timescale 1ns/100ps

module tb();
reg [7:0] snd;
reg clk;

initial begin
$dumpvars;
$timeformat(-9, 1, "ns", 6);
end

initial begin
clk = 0;
snd = 0;
$display("INFO %t clk: %b send: %h", $time, clk, snd);
#30 $finish;
end

always @(posedge clk) begin
#0.3 snd = snd + 1;
$display("INFO %t clk: %b send: %h", $time, clk, snd);
#0.3 snd = snd + 1;
$display("INFO %t clk: %b send: %h", $time, clk, snd);
#0.3 snd = snd + 1;
$display("INFO %t clk: %b send: %h", $time, clk, snd);
#0.3 snd = snd + 1;
$display("INFO %t clk: %b send: %h", $time, clk, snd);
end

always begin
#10 clk = ~clk;
end

endmodule


Why is the output like:

INFO 0.0ns clk: 0 send: 00
INFO 10.0ns clk: 1 send: 01
INFO 11.0ns clk: 1 send: 02
INFO 11.0ns clk: 1 send: 03
INFO 11.0ns clk: 1 send: 04


And not:

INFO 0.0ns clk: 0 send: 00
INFO 10.3ns clk: 1 send: 01
INFO 10.6ns clk: 1 send: 02
INFO 10.9ns clk: 1 send: 03
INFO 11.2ns clk: 1 send: 04


The $dumpvars dump file has it right (VCS and Verilog-XL):

#103
b00000001 !
#106
b00000010 !
#109
b00000011 !
#112
b00000100 !


Thanks,
/Ed